WARP APIs: radio_controller_basic.c Source File

00001 // Copyright (c) 2006 Rice University
00002 // All Rights Reserved
00003 // This code is covered by the Rice-WARP license
00004 // See http://warp.rice.edu/license/ for details
00005 
00017 /***************************** Include Files *******************************/
00018 
00019 #include "radio_controller_basic.h"
00020 
00021 /****************************** Functions **********************************/
00022 
00033 void WarpRadio_v1_Reset(unsigned int* baseaddress, unsigned int clkRatio) {
00034 
00035         radio_controller_baseaddr = baseaddress;
00036 
00037         RADIO_CONTROLLER_mWriteSlaveReg5((volatile)radio_controller_baseaddr, 0x3410);                  // Set the value of the Control Register to 0x00003410 for DACs
00038         RADIO_CONTROLLER_mWriteSlaveReg6((volatile)radio_controller_baseaddr, clkRatio);                // Set the value for the Divider Register to 0x00000001
00039 
00040         RADIO_CONTROLLER_mWriteSlaveReg7((volatile)radio_controller_baseaddr, (SLAVEMASKDAC & (RADIO1_ADDR | RADIO2_ADDR | RADIO3_ADDR | RADIO4_ADDR)));                // Select all DACs
00041 
00042         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, RAD_TX_DAC_RESET_MASK); // Turn on DacReset
00043         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~(RAD_TX_DAC_RESET_MASK))); // Turn off DacReset
00044 
00045         transmitdac(0x0004);                                    // Transmit a value of 0x04 for Register 0 for DAC to use only 1 refernce register
00046 
00047 
00048         RADIO_CONTROLLER_mWriteSlaveReg5((volatile)radio_controller_baseaddr, 0x3412);                  // Set the value of the Control Register to 0x00003412 for Radio
00049         RADIO_CONTROLLER_mWriteSlaveReg6((volatile)radio_controller_baseaddr, clkRatio-1);              // Set the value for the Divider Register to 0x00000000
00050 
00051         RADIO_CONTROLLER_mWriteSlaveReg7((volatile)radio_controller_baseaddr, (SLAVEMASK & (RADIO1_ADDR | RADIO2_ADDR | RADIO3_ADDR | RADIO4_ADDR)));           // Select the radios that will be affected by this function call in store in Slave Select
00052 
00053         // Go through reset procedure
00054         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, ~(RAD_SHDN_MASK | RAD_SHDN_CON_MASK | RAD_TXEN_MASK | RAD_TXEN_CON_MASK | RAD_RXEN_MASK | RAD_RXEN_CON_MASK | RAD_RXHP_MASK | RAD_RXHP_CON_MASK));
00055         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) | RAD_SHDN_MASK)); // Asset Shutdown
00056         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) | (RAD_TXEN_MASK | RAD_RXEN_MASK))); // Enable Rx and Tx
00057         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) & ~(RAD_TXEN_MASK | RAD_RXEN_MASK))); // Disable Rx and Tx
00058         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) & ~RAD_SHDN_MASK)); // De-asset Shutdown
00059 
00060         // Start initialization
00061         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) | RAD_RXHP_CON_MASK)); // Set RxHP control to HW
00062         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) | RAD_24PA_MASK)); // Antsw[1] to 1 and enable 2.4GHz amplifier
00063         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~RAD_ADC_RX_DCS_MASK)); // DCS to 0
00064         RADIO_CONTROLLER_mWriteSlaveReg2((volatile)radio_controller_baseaddr, 0x00000000 & ~(RAD_ADC_RX_PWDNA_MASK | RAD_ADC_RX_PWDNB_MASK | RAD_RSSI_ADC_SLEEP_MASK)); // Enable all ADCs
00065 
00066         transmit(0x0C218);                      // Set value of 0x0C21 to register 8 in the radio
00067         REG_RAD1_RX_CONTROL = (short)0x0C21;                    // Update local copies of the registers in the radio
00068         REG_RAD2_RX_CONTROL = (short)0x0C21;
00069         REG_RAD3_RX_CONTROL = (short)0x0C21;
00070         REG_RAD4_RX_CONTROL = (short)0x0C21;
00071 
00072         // Setup for 20MHz radio reference clock
00073         transmit(0x18225);
00074         REG_RAD1_BAND_SELECT = (short)0x1822;
00075         REG_RAD2_BAND_SELECT = (short)0x1822;
00076         REG_RAD3_BAND_SELECT = (short)0x1822;
00077         REG_RAD4_BAND_SELECT = (short)0x1822;
00078 
00079         // Setup for 40MHz radio reference clock
00080         //transmit(0x18245);
00081         //REG_RAD1_BAND_SELECT = (short)0x1824;
00082         //REG_RAD2_BAND_SELECT = (short)0x1824;
00083         //REG_RAD3_BAND_SELECT = (short)0x1824;
00084         //REG_RAD4_BAND_SELECT = (short)0x1824;
00085 
00086         unsigned int reg2 = REG_RAD1_STANDBY | 0x2000;
00087         transmit(((reg2<<4)+0x0002));
00088         REG_RAD1_STANDBY = (short)reg2;
00089         REG_RAD2_STANDBY = (short)reg2;
00090         REG_RAD3_STANDBY = (short)reg2;
00091         REG_RAD4_STANDBY = (short)reg2;
00092 
00093         unsigned int reg5 = REG_RAD1_BAND_SELECT | 0x2000;
00094         transmit(((reg5<<4)+0x0005));
00095         REG_RAD1_BAND_SELECT = (short)reg5;
00096         REG_RAD2_BAND_SELECT = (short)reg5;
00097         REG_RAD3_BAND_SELECT = (short)reg5;
00098         REG_RAD4_BAND_SELECT = (short)reg5;
00099 
00100         unsigned int reg9 = REG_RAD1_TX_LINEARITY | 0x0003;
00101         transmit(((reg9<<4)+0x0009));
00102         REG_RAD1_TX_LINEARITY = (short)reg9;
00103         REG_RAD2_TX_LINEARITY = (short)reg9;
00104         REG_RAD3_TX_LINEARITY = (short)reg9;
00105         REG_RAD4_TX_LINEARITY = (short)reg9;
00106 
00107         //Setup the deault TxTiming values for all four radios
00108         //Field assignments in these four registers (everything endian-swapped):
00109         // bits[0:7]: delay for gain ramp start (default = 100 cycles)
00110         // bits[8:15] delay for power amp start (default = 0 cycles)
00111         // bits[16:23] delay for radio TxEn start (default = 0 cycles)
00112         RADIO_CONTROLLER_mWriteSlaveReg13((volatile)radio_controller_baseaddr,(unsigned int)( (100 << 24) + (0 << 16) + (0 << 8) ) );
00113         RADIO_CONTROLLER_mWriteSlaveReg14((volatile)radio_controller_baseaddr,(unsigned int)( (100 << 24) + (0 << 16) + (0 << 8) ) );
00114         RADIO_CONTROLLER_mWriteSlaveReg15((volatile)radio_controller_baseaddr,(unsigned int)( (100 << 24) + (0 << 16) + (0 << 8) ) );
00115         RADIO_CONTROLLER_mWriteSlaveReg16((volatile)radio_controller_baseaddr,(unsigned int)( (100 << 24) + (0 << 16) + (0 << 8) ) );
00116 
00117         //Setup the deault TxGainTiming values for all four radios
00118         // bits[0:5]: target gain (default = 0x3f = max Tx gain)
00119         // bits[6:9]: gain step (default = 0xF = max gain step)
00120         // bits[10:13]: gain time step (default = 2 = min gain time step)
00121         // bits[16:27]: delay for TxStart (default = 200 cycles)
00122         RADIO_CONTROLLER_mWriteSlaveReg9((volatile)radio_controller_baseaddr,(unsigned int)((0x3F << 26) | (0xF << 22) | ((2) << 18) | (200 << 4)));
00123         RADIO_CONTROLLER_mWriteSlaveReg10((volatile)radio_controller_baseaddr,(unsigned int)((0x3F << 26) | (0xF << 22) | ((2) << 18) | (200 << 4)));
00124         RADIO_CONTROLLER_mWriteSlaveReg11((volatile)radio_controller_baseaddr,(unsigned int)((0x3F << 26) | (0xF << 22) | ((2) << 18) | (200 << 4)));
00125         RADIO_CONTROLLER_mWriteSlaveReg12((volatile)radio_controller_baseaddr,(unsigned int)((0x3F << 26) | (0xF << 22) | ((2) << 18) | (200 << 4)));
00126 
00127         return;
00128 }
00129 
00138 void WarpRadio_v1_TxEnable(unsigned int radios) {
00139 
00140         unsigned int tmpReg = 0;
00141         
00142         //Swap the antenna switch to map the Tx port to antenna port 1
00143         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) | (radios & RAD_ANTSW_MASK)));
00144 
00145         //Read the current radio controller Tx/Rx mode register into a temporary variable
00146         tmpReg = RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr);
00147 
00148         //De-assert the RxEnable bits for the selected radios (no harm if they're already disabled)
00149         tmpReg = tmpReg & ~(radios & RAD_RXEN_MASK);
00150 
00151         //Assert the TxEnable bits for the selected radios (no harm if they're already enabled)
00152         tmpReg = tmpReg | (radios & RAD_TXEN_MASK);
00153 
00154         //Write the update register contents back to the radio controller
00155         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, tmpReg);
00156 
00157         return;
00158 }
00159 
00160 
00168 void WarpRadio_v1_RxEnable(unsigned int radios) {
00169 
00170         unsigned int tmpReg = 0;
00171         
00172         //Swap the antenna switch to map the Rx port to antenna port 1
00173         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~(radios & RAD_ANTSW_MASK)));
00174 
00175         //Read the current radio controller Tx/Rx mode register into a temporary variable
00176         tmpReg = RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr);
00177 
00178         //De-assert the TxEnable bits for the selected radios (no harm if they're already disabled)
00179         tmpReg = tmpReg & ~(radios & RAD_TXEN_MASK);
00180 
00181         //Assert the RxEnable bits for the selected radios (no harm if they're already enabled)
00182         tmpReg = tmpReg | (radios & RAD_RXEN_MASK);
00183 
00184         //Write the update register contents back to the radio controller
00185         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, tmpReg);
00186 
00187         return;
00188 }
00189 
00197 void WarpRadio_v1_TxRxDisable(unsigned int radios) {
00198 
00199         RADIO_CONTROLLER_mWriteSlaveReg0((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg0((volatile)radio_controller_baseaddr) & ~(radios & (RAD_TXEN_MASK | RAD_RXEN_MASK)))); // Disable Tx and Rx
00200 }
00201 
00226 int WarpRadio_v1_SetCenterFreq2GHz(char freqset, unsigned int radios) {
00227 
00228         RADIO_CONTROLLER_mWriteSlaveReg7((volatile)radio_controller_baseaddr, (SLAVEMASK & radios));                    // Select Radios affected by this function
00229 
00230         unsigned int reg3;
00231         unsigned int reg4;
00232         unsigned int reg5;
00233         int retval;                                                     // Return value from the function
00234         unsigned int mask2g = 0xFF3E;           // Mask to set frequency band to 2.4Ghz
00235 
00236         switch(freqset) {                                       // Switch on the frequency set given as input.
00237                 case(1) : {
00238                         reg3 = 0x00A03;                         // Set a value of 0x00A0 for Register 3
00239                         reg4 = 0x33334;                         // Set a value of 0x3333 for Register 4
00240                         retval = 2412;                          // Set the return value to the frequency that has been set.
00241                         break;
00242                 }
00243                 case(2) : {
00244                         reg3 = 0x20A13;
00245                         reg4 = 0x08884;
00246                         retval = 2417;
00247                         break;
00248                 }
00249                 case(3) : {
00250                         reg3 = 0x30A13;
00251                         reg4 = 0x1DDD4;
00252                         retval = 2422;
00253                         break;
00254                 }
00255                 case(4) : {
00256                         reg3 = 0x00A13;
00257                         reg4 = 0x33334;
00258                         retval = 2427;
00259                         break;
00260                 }
00261                 case(5) : {
00262                         reg3 = 0x20A23;
00263                         reg4 = 0x08884;
00264                         retval = 2432;
00265                         break;
00266                 }
00267                 case(6) : {
00268                         reg3 = 0x30A23;
00269                         reg4 = 0x1DDD4;
00270                         retval = 2437;
00271                         break;
00272                 }
00273                 case(7) : {
00274                         reg3 = 0x00A23;
00275                         reg4 = 0x33334;
00276                         retval = 2442;
00277                         break;
00278                 }
00279                 case(8) : {
00280                         reg3 = 0x20A33;
00281                         reg4 = 0x08884;
00282                         retval = 2447;
00283                         break;
00284                 }
00285                 case(9) : {
00286                         reg3 = 0x30A33;
00287                         reg4 = 0x1DDD4;
00288                         retval = 2452;
00289                         break;
00290                 }
00291                 case(10) : {
00292                         reg3 = 0x00A33;
00293                         reg4 = 0x33334;
00294                         retval = 2457;
00295                         break;
00296                 }
00297                 case(11) : {
00298                         reg3 = 0x20A43;
00299                         reg4 = 0x08884;
00300                         retval = 2462;
00301                         break;
00302                 }
00303                 case(12) : {
00304                         reg3 = 0x30A43;
00305                         reg4 = 0x1DDD4;
00306                         retval = 2467;
00307                         break;
00308                 }
00309                 case(13) : {
00310                         reg3 = 0x00A43;
00311                         reg4 = 0x33334;
00312                         retval = 2472;
00313                         break;
00314                 }
00315                 case(14) : {
00316                         reg3 = 0x10A53;
00317                         reg4 = 0x26664;
00318                         retval = 2484;
00319                         break;
00320                 }
00321                 default : {
00322                         retval = INVALID_FREQ;
00323                 }
00324         }
00325 
00326         if(retval != -1) {                                              // Check if an invalid freqency set has been provided and if so do not change freqency
00327 
00328                 transmit(reg3);                 // Transmit the new register 3 value
00329                 transmit(reg4);                 // Transmit the new register 4 value
00330 
00331                 reg3 = reg3>>4;                                         // Bit shift the register values to the right and remove the register number from the
00332                 reg4 = reg4>>4;                                         // value.
00333 
00334                 if((radios & RAD1MASK) > 0) {   // Check if the Slave is in use
00335 
00336                         reg5 = REG_RAD1_BAND_SELECT & mask2g;                                   // Pick up local copy of the register and set the band to 2.4Ghz
00337 
00338                         transRadio(0x0001, ((reg5<<4)+0x0005));         // Transmit new register 5 value and add the register number as last 4 bits
00339 
00340                         REG_RAD1_BAND_SELECT = (short)reg5;                                             // Set local copies of registers to new values.
00341                         REG_RAD1_INTEGER_DIVIDER_RATIO = (short)reg3;
00342                         REG_RAD1_FRACTIONAL_DIVIDER_RATIO = (short)reg4;
00343                 }
00344                 if((radios & RAD2MASK) > 0) {   // Check if the Slave is in use
00345 
00346                         reg5 = REG_RAD2_BAND_SELECT & mask2g;                                   // Pick up local copy of the register and set the band to 2.4Ghz
00347 
00348                         transRadio(0x0002, ((reg5<<4)+0x0005));         // Transmit new register 5 value and add the register number as last 4 bits
00349 
00350                         REG_RAD2_BAND_SELECT = (short)reg5;                                             // Set local copies of registers to new values.
00351                         REG_RAD2_INTEGER_DIVIDER_RATIO = (short)reg3;
00352                         REG_RAD2_FRACTIONAL_DIVIDER_RATIO = (short)reg4;
00353                 }
00354                 if((radios & RAD3MASK) > 0) {   // Check if the Slave is in use
00355 
00356                         reg5 = REG_RAD3_BAND_SELECT & mask2g;                                   // Pick up local copy of the register and set the band to 2.4Ghz
00357 
00358                         transRadio(0x0004, ((reg5<<4)+0x0005));         // Transmit new register 5 value and add the register number as last 4 bits
00359 
00360                         REG_RAD3_BAND_SELECT = (short)reg5;                                             // Set local copies of registers to new values.
00361                         REG_RAD3_INTEGER_DIVIDER_RATIO = (short)reg3;
00362                         REG_RAD3_FRACTIONAL_DIVIDER_RATIO = (short)reg4;
00363                 }
00364                 if((radios & RAD4MASK) > 0) {   // Check if the Slave is in use
00365 
00366                         reg5 = REG_RAD4_BAND_SELECT & mask2g;                                   // Pick up local copy of the register and set the band to 2.4Ghz
00367 
00368                         transRadio(0x0008, ((reg5<<4)+0x0005));         // Transmit new register 5 value and add the register number as last 4 bits
00369 
00370                         REG_RAD4_BAND_SELECT = (short)reg5;                                             // Set local copies of registers to new values.
00371                         REG_RAD4_INTEGER_DIVIDER_RATIO = (short)reg3;
00372                         REG_RAD4_FRACTIONAL_DIVIDER_RATIO = (short)reg4;
00373                 }
00374         }
00375 
00376 
00377         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~(radios & RAD_5PA_MASK))); // Disable 5GHz amp
00378         RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) | (radios & RAD_24PA_MASK))); // Enable 2.4GHz amp
00379 
00380         return retval;          // Return either the new freqency that has been set or return -1 to indicate that the frequency set given was invalid
00381 }
00382 
00383 
00391 char WarpRadio_v1_DIPSW(unsigned int radio) {
00392 
00393         if((radio & RAD1MASK) > 0) {            // Check to make sure if Radio 1 is being used
00394                 return ((RADIO_CONTROLLER_mReadSlaveReg3((volatile)radio_controller_baseaddr) & RAD_DIPSW_L_MASK) >> 10);
00395         }
00396         else if((radio & RAD2MASK) > 0) {               // Check to make sure if Radio 2 is being used
00397                 return ((RADIO_CONTROLLER_mReadSlaveReg3((volatile)radio_controller_baseaddr) & RAD_DIPSW_H_MASK) >> 26);
00398         }
00399         else if((radio & RAD3MASK) > 0) {               // Check to make sure if Radio 3 is being used
00400                 return ((RADIO_CONTROLLER_mReadSlaveReg4((volatile)radio_controller_baseaddr) & RAD_DIPSW_L_MASK) >> 10);
00401         }
00402         else if((radio & RAD4MASK) > 0) {               // Check to make sure if Radio 4 is being used
00403                 return ((RADIO_CONTROLLER_mReadSlaveReg4((volatile)radio_controller_baseaddr) & RAD_DIPSW_H_MASK) >> 26);
00404         }
00405         else {
00406                 return 0;
00407         }
00408 }
00409 
00422 int WarpRadio_v1_DACOffsetAdj(char chan, short value, unsigned int radios) {
00423 
00424         RADIO_CONTROLLER_mWriteSlaveReg5((volatile)radio_controller_baseaddr, 0x3410);                  // Set the value of the Control Register to 0x00003410 for DACs
00425         RADIO_CONTROLLER_mWriteSlaveReg6((volatile)radio_controller_baseaddr, 0x00000001);              // Set the value for the Divider Register to 0x00000001
00426 
00427         RADIO_CONTROLLER_mWriteSlaveReg7((volatile)radio_controller_baseaddr, (SLAVEMASKDAC & radios));         // Select the dacs that need to be affected
00428 
00429         if (value > 1023 || value < -1024) {                    // Make sure the value is in range.
00430                 return OUT_OF_RANGE;
00431         }
00432 
00433         short reg8;
00434         if (value < 0) {                                                                // If the value is negative then store set the first bit of second register
00435                 reg8 = 0x0080;                                                          // to 1
00436         }
00437         else {
00438                 reg8 = 0x0000;                                                          // Or if positive set it to 0.
00439         }
00440 
00441         value = abs(value);
00442 
00443         short reg7 = ((value & 0x03FC) >> 2);                   // b9:b2 of the value are the 8 bits in the first register
00444         reg8 = reg8 + (value & 0x0003);                                 // b1:b0 of the value are the last 2 bits in the second register
00445 
00446         if (chan == ICHAN) {
00447                 transmitdac((0x0700 + reg7));           // if I channel then store the first register to Register 7
00448                 transmitdac((0x0800 + reg8));           // and the second register to Register 8
00449         }
00450         else if (chan == QCHAN) {
00451                 transmitdac((0x0B00 + reg7));           // if I channel then store the first register to Register B
00452                 transmitdac((0x0C00 + reg8));           // and the second register to Register C
00453         }
00454         else {
00455                 return INVALID_MODE;
00456         }
00457 
00458         RADIO_CONTROLLER_mWriteSlaveReg5((volatile)radio_controller_baseaddr, 0x3412);                  // Set the value of the Control Register to 0x00003412 for Radio
00459         RADIO_CONTROLLER_mWriteSlaveReg6((volatile)radio_controller_baseaddr, 0x00000000);              // Set the value for the Divider Register to 0x00000000
00460 
00461         return WARP_SUCCESS;
00462 }
00463