radio_prototypes.h

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00001 // Copyright (c) 2006 Rice University
00002 // All Rights Reserved
00003 // This code is covered by the Rice-WARP license
00004 // See http://warp.rice.edu/license/ for details
00005 
00019 #ifndef RADIO_PROTOTYPES_H
00020 #define RADIO_PROTOTYPES_H
00021 
00022 /***************************** Include Files *******************************/
00023 
00024 #include "xbasic_types.h"
00025 #include "xstatus.h"
00026 #include "xio.h"
00027 
00028 /************************** Constant Definitions ***************************/
00029 
00030 
00031 /*
00032  * User Logic Slave Space Offsets
00033  * -- SLAVE_REG0 : user logic slave module register 0
00034  * -- SLAVE_REG1 : user logic slave module register 1
00035  * -- SLAVE_REG2 : user logic slave module register 2
00036  * -- SLAVE_REG3 : user logic slave module register 3
00037  * -- SLAVE_REG4 : user logic slave module register 4
00038  * -- SLAVE_REG5 : user logic slave module register 5
00039  * -- SLAVE_REG6 : user logic slave module register 6
00040  * -- SLAVE_REG7 : user logic slave module register 7
00041  * -- SLAVE_REG8 : user logic slave module register 8
00042  * -- SLAVE_REG9 : user logic slave module register 9
00043  * -- SLAVE_REG10 : user logic slave module register 10
00044  * -- SLAVE_REG11 : user logic slave module register 11
00045  * -- SLAVE_REG12 : user logic slave module register 12
00046  * -- SLAVE_REG13 : user logic slave module register 13
00047  * -- SLAVE_REG14 : user logic slave module register 14
00048  * -- SLAVE_REG15 : user logic slave module register 15
00049  * -- SLAVE_REG16 : user logic slave module register 16
00050  */
00051 #define RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET (0x00000000)
00052 #define RADIO_CONTROLLER_SLAVE_REG0_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000000)
00053 #define RADIO_CONTROLLER_SLAVE_REG1_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000004)
00054 #define RADIO_CONTROLLER_SLAVE_REG2_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000008)
00055 #define RADIO_CONTROLLER_SLAVE_REG3_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x0000000C)
00056 #define RADIO_CONTROLLER_SLAVE_REG4_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000010)
00057 #define RADIO_CONTROLLER_SLAVE_REG5_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000014)
00058 #define RADIO_CONTROLLER_SLAVE_REG6_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000018)
00059 #define RADIO_CONTROLLER_SLAVE_REG7_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x0000001C)
00060 #define RADIO_CONTROLLER_SLAVE_REG8_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000020)
00061 #define RADIO_CONTROLLER_SLAVE_REG9_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000024)
00062 #define RADIO_CONTROLLER_SLAVE_REG10_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000028)
00063 #define RADIO_CONTROLLER_SLAVE_REG11_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x0000002C)
00064 #define RADIO_CONTROLLER_SLAVE_REG12_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000030)
00065 #define RADIO_CONTROLLER_SLAVE_REG13_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000034)
00066 #define RADIO_CONTROLLER_SLAVE_REG14_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000038)
00067 #define RADIO_CONTROLLER_SLAVE_REG15_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x0000003C)
00068 #define RADIO_CONTROLLER_SLAVE_REG16_OFFSET (RADIO_CONTROLLER_USER_SLAVE_SPACE_OFFSET + 0x00000040)
00069 
00070 /**************************** Type Definitions *****************************/
00071 
00072 
00073 /***************** Macros (Inline Functions) Definitions *******************/
00074 
00075 /*
00076  *
00077  * Write a value to a RADIO_CONTROLLER register. A 32 bit write is performed.
00078  * If the component is implemented in a smaller width, only the least
00079  * significant data is written.
00080  *
00081  * @param   BaseAddress is the base address of the RADIO_CONTROLLER device.
00082  * @param   RegOffset is the register offset from the base to write to.
00083  * @param   Data is the data written to the register.
00084  *
00085  * @return  None.
00086  *
00087  * @note
00088  * C-style signature:
00089  *      void RADIO_CONTROLLER_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
00090  *
00091  */
00092 #define RADIO_CONTROLLER_mWriteReg(BaseAddress, RegOffset, Data) \
00093         XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
00094 
00095 /*
00096  *
00097  * Read a value from a RADIO_CONTROLLER register. A 32 bit read is performed.
00098  * If the component is implemented in a smaller width, only the least
00099  * significant data is read from the register. The most significant data
00100  * will be read as 0.
00101  *
00102  * @param   BaseAddress is the base address of the RADIO_CONTROLLER device.
00103  * @param   RegOffset is the register offset from the base to write to.
00104  *
00105  * @return  Data is the data from the register.
00106  *
00107  * @note
00108  * C-style signature:
00109  *      Xuint32 RADIO_CONTROLLER_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
00110  *
00111  */
00112 #define RADIO_CONTROLLER_mReadReg(BaseAddress, RegOffset) \
00113         XIo_In32((BaseAddress) + (RegOffset))
00114 
00115 
00116 /*
00117  *
00118  * Write/Read value to/from RADIO_CONTROLLER user logic slave registers.
00119  *
00120  * @param   BaseAddress is the base address of the RADIO_CONTROLLER device.
00121  * @param   Value is the data written to the register.
00122  *
00123  * @return  Data is the data from the user logic slave register.
00124  *
00125  * @note
00126  * C-style signature:
00127  *      Xuint32 RADIO_CONTROLLER_mReadSlaveRegn(Xuint32 BaseAddress)
00128  *
00129  */
00130 #define RADIO_CONTROLLER_mWriteSlaveReg0(BaseAddress, Value) \
00131         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG0_OFFSET), (Xuint32)(Value))
00132 #define RADIO_CONTROLLER_mWriteSlaveReg1(BaseAddress, Value) \
00133         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG1_OFFSET), (Xuint32)(Value))
00134 #define RADIO_CONTROLLER_mWriteSlaveReg2(BaseAddress, Value) \
00135         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG2_OFFSET), (Xuint32)(Value))
00136 #define RADIO_CONTROLLER_mWriteSlaveReg3(BaseAddress, Value) \
00137         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG3_OFFSET), (Xuint32)(Value))
00138 #define RADIO_CONTROLLER_mWriteSlaveReg4(BaseAddress, Value) \
00139         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG4_OFFSET), (Xuint32)(Value))
00140 #define RADIO_CONTROLLER_mWriteSlaveReg5(BaseAddress, Value) \
00141         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG5_OFFSET), (Xuint32)(Value))
00142 #define RADIO_CONTROLLER_mWriteSlaveReg6(BaseAddress, Value) \
00143         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG6_OFFSET), (Xuint32)(Value))
00144 #define RADIO_CONTROLLER_mWriteSlaveReg7(BaseAddress, Value) \
00145         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG7_OFFSET), (Xuint32)(Value))
00146 #define RADIO_CONTROLLER_mWriteSlaveReg8(BaseAddress, Value) \
00147         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG8_OFFSET), (Xuint32)(Value))
00148 #define RADIO_CONTROLLER_mWriteSlaveReg9(BaseAddress, Value) \
00149         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG9_OFFSET), (Xuint32)(Value))
00150 #define RADIO_CONTROLLER_mWriteSlaveReg10(BaseAddress, Value) \
00151         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG10_OFFSET), (Xuint32)(Value))
00152 #define RADIO_CONTROLLER_mWriteSlaveReg11(BaseAddress, Value) \
00153         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG11_OFFSET), (Xuint32)(Value))
00154 #define RADIO_CONTROLLER_mWriteSlaveReg12(BaseAddress, Value) \
00155         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG12_OFFSET), (Xuint32)(Value))
00156 #define RADIO_CONTROLLER_mWriteSlaveReg13(BaseAddress, Value) \
00157         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG13_OFFSET), (Xuint32)(Value))
00158 #define RADIO_CONTROLLER_mWriteSlaveReg14(BaseAddress, Value) \
00159         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG14_OFFSET), (Xuint32)(Value))
00160 #define RADIO_CONTROLLER_mWriteSlaveReg15(BaseAddress, Value) \
00161         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG15_OFFSET), (Xuint32)(Value))
00162 #define RADIO_CONTROLLER_mWriteSlaveReg16(BaseAddress, Value) \
00163         XIo_Out32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG16_OFFSET), (Xuint32)(Value))
00164 
00165 #define RADIO_CONTROLLER_mReadSlaveReg0(BaseAddress) \
00166         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG0_OFFSET))
00167 #define RADIO_CONTROLLER_mReadSlaveReg1(BaseAddress) \
00168         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG1_OFFSET))
00169 #define RADIO_CONTROLLER_mReadSlaveReg2(BaseAddress) \
00170         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG2_OFFSET))
00171 #define RADIO_CONTROLLER_mReadSlaveReg3(BaseAddress) \
00172         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG3_OFFSET))
00173 #define RADIO_CONTROLLER_mReadSlaveReg4(BaseAddress) \
00174         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG4_OFFSET))
00175 #define RADIO_CONTROLLER_mReadSlaveReg5(BaseAddress) \
00176         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG5_OFFSET))
00177 #define RADIO_CONTROLLER_mReadSlaveReg6(BaseAddress) \
00178         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG6_OFFSET))
00179 #define RADIO_CONTROLLER_mReadSlaveReg7(BaseAddress) \
00180         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG7_OFFSET))
00181 #define RADIO_CONTROLLER_mReadSlaveReg8(BaseAddress) \
00182         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG8_OFFSET))
00183 #define RADIO_CONTROLLER_mReadSlaveReg9(BaseAddress) \
00184         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG9_OFFSET))
00185 #define RADIO_CONTROLLER_mReadSlaveReg10(BaseAddress) \
00186         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG10_OFFSET))
00187 #define RADIO_CONTROLLER_mReadSlaveReg11(BaseAddress) \
00188         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG11_OFFSET))
00189 #define RADIO_CONTROLLER_mReadSlaveReg12(BaseAddress) \
00190         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG12_OFFSET))
00191 #define RADIO_CONTROLLER_mReadSlaveReg13(BaseAddress) \
00192         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG13_OFFSET))
00193 #define RADIO_CONTROLLER_mReadSlaveReg14(BaseAddress) \
00194         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG14_OFFSET))
00195 #define RADIO_CONTROLLER_mReadSlaveReg15(BaseAddress) \
00196         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG15_OFFSET))
00197 #define RADIO_CONTROLLER_mReadSlaveReg16(BaseAddress) \
00198         XIo_In32((BaseAddress) + (RADIO_CONTROLLER_SLAVE_REG16_OFFSET))
00199 
00200 /********************** Radio Controller Definitions ***********************/
00201 
00203 #define RADIO1_ADDR 0x11111111
00205 #define RADIO2_ADDR 0x22222222
00207 #define RADIO3_ADDR 0x44444444
00209 #define RADIO4_ADDR 0x88888888
00210 
00211 #define RAD1MASK 0x0001
00212 #define RAD2MASK 0x0002
00213 #define RAD3MASK 0x0004
00214 #define RAD4MASK 0x0008
00215 #define SLAVEMASK 0x000F
00216 #define SLVREGRDMSK 0x002063EF
00217 #define DAC1MASK 0x0010
00218 #define DAC2MASK 0x0020
00219 #define DAC3MASK 0x0040
00220 #define DAC4MASK 0x0080
00221 #define SLAVEMASKDAC 0x00F0
00222 
00224 #define WARP_SUCCESS 0
00225 #define NOT_IN_CALIBRATION -2
00227 #define INVALID_GAIN -1
00229 #define INVALID_FREQ -1
00231 #define INVALID_MODE -1
00233 #define OUT_OF_RANGE -2
00235 #define ICHAN 1
00237 #define QCHAN 2
00238 
00239 /*-- Masks for all slave register bit locations --*/
00240 
00241 #define RAD_SHDN_MASK                           0x0000000F
00242 #define RAD_SHDN_CON_MASK                       0x000000F0
00243 #define RAD_TXEN_MASK                           0x00000F00
00244 #define RAD_TXEN_CON_MASK                       0x0000F000
00245 #define RAD_RXEN_MASK                           0x000F0000
00246 #define RAD_RXEN_CON_MASK                       0x00F00000
00247 #define RAD_RXHP_MASK                           0x0F000000
00248 #define RAD_RXHP_CON_MASK                       0xF0000000
00249 #define RAD_24PA_MASK                           0x0000000F
00250 #define RAD_5PA_MASK                            0x000000F0
00251 #define RAD_LD_MASK                                     0x00000F00
00252 #define RAD_ANTSW_MASK                          0x000F0000
00253 #define RAD_TX_DAC_RESET_MASK           0x00F00000
00254 #define RAD_ADC_RX_DCS_MASK                     0x0F000000
00255 #define RAD_ADC_RX_DFS_MASK                     0xF0000000
00256 #define RAD_ADC_RX_OTRA_MASK            0x0000000F
00257 #define RAD_ADC_RX_OTRB_MASK            0x000000F0
00258 #define RAD_ADC_RX_PWDNA_MASK           0x00000F00
00259 #define RAD_ADC_RX_PWDNB_MASK           0x0000F000
00260 #define RAD_RSSI_ADC_SLEEP_MASK         0x000F0000
00261 #define RAD_RSSI_ADC_OTR_MASK           0x00F00000
00262 #define RAD_RSSI_ADC_HIZ_MASK           0x0F000000
00263 #define RAD_RSSI_ADC_CLAMP_MASK         0xF0000000
00264 #define RAD_DIPSW_L_MASK                        0x00003C00
00265 #define RAD_DIPSW_H_MASK                        0x3C000000
00266 #define RAD_TX_DAC_PLL_LOCK_MASK        0x80008000
00267 #define RAD_RSSI_ADC_D_L_MASK           0x000003FF
00268 #define RAD_RSSI_ADC_D_H_MASK           0x03FF0000
00269 
00270 /*-- Local copies of radio registers --*/
00271 
00272 // RADIO 1
00273 extern unsigned short REG_RAD1_REGISTER_0;
00274 extern unsigned short REG_RAD1_REGISTER_1;
00275 extern unsigned short REG_RAD1_STANDBY;
00276 extern unsigned short REG_RAD1_INTEGER_DIVIDER_RATIO;
00277 extern unsigned short REG_RAD1_FRACTIONAL_DIVIDER_RATIO;
00278 extern unsigned short REG_RAD1_BAND_SELECT;
00279 extern unsigned short REG_RAD1_CALIBRATION;
00280 extern unsigned short REG_RAD1_LOWPASS_FILTER;
00281 extern unsigned short REG_RAD1_RX_CONTROL;
00282 extern unsigned short REG_RAD1_TX_LINEARITY;
00283 extern unsigned short REG_RAD1_PA_BIAS_DAC;
00284 extern unsigned short REG_RAD1_RX_GAIN;
00285 extern unsigned short REG_RAD1_TX_VGA_GAIN;
00286 
00287 // RADIO 2
00288 extern unsigned short REG_RAD2_REGISTER_0;
00289 extern unsigned short REG_RAD2_REGISTER_1;
00290 extern unsigned short REG_RAD2_STANDBY;
00291 extern unsigned short REG_RAD2_INTEGER_DIVIDER_RATIO;
00292 extern unsigned short REG_RAD2_FRACTIONAL_DIVIDER_RATIO;
00293 extern unsigned short REG_RAD2_BAND_SELECT;
00294 extern unsigned short REG_RAD2_CALIBRATION;
00295 extern unsigned short REG_RAD2_LOWPASS_FILTER;
00296 extern unsigned short REG_RAD2_RX_CONTROL;
00297 extern unsigned short REG_RAD2_TX_LINEARITY;
00298 extern unsigned short REG_RAD2_PA_BIAS_DAC;
00299 extern unsigned short REG_RAD2_RX_GAIN;
00300 extern unsigned short REG_RAD2_TX_VGA_GAIN;
00301 
00302 // RADIO 3
00303 extern unsigned short REG_RAD3_REGISTER_0;
00304 extern unsigned short REG_RAD3_REGISTER_1;
00305 extern unsigned short REG_RAD3_STANDBY;
00306 extern unsigned short REG_RAD3_INTEGER_DIVIDER_RATIO;
00307 extern unsigned short REG_RAD3_FRACTIONAL_DIVIDER_RATIO;
00308 extern unsigned short REG_RAD3_BAND_SELECT;
00309 extern unsigned short REG_RAD3_CALIBRATION;
00310 extern unsigned short REG_RAD3_LOWPASS_FILTER;
00311 extern unsigned short REG_RAD3_RX_CONTROL;
00312 extern unsigned short REG_RAD3_TX_LINEARITY;
00313 extern unsigned short REG_RAD3_PA_BIAS_DAC;
00314 extern unsigned short REG_RAD3_RX_GAIN;
00315 extern unsigned short REG_RAD3_TX_VGA_GAIN;
00316 
00317 // RADIO 4
00318 extern unsigned short REG_RAD4_REGISTER_0;
00319 extern unsigned short REG_RAD4_REGISTER_1;
00320 extern unsigned short REG_RAD4_STANDBY;
00321 extern unsigned short REG_RAD4_INTEGER_DIVIDER_RATIO;
00322 extern unsigned short REG_RAD4_FRACTIONAL_DIVIDER_RATIO;
00323 extern unsigned short REG_RAD4_BAND_SELECT;
00324 extern unsigned short REG_RAD4_CALIBRATION;
00325 extern unsigned short REG_RAD4_LOWPASS_FILTER;
00326 extern unsigned short REG_RAD4_RX_CONTROL;
00327 extern unsigned short REG_RAD4_TX_LINEARITY;
00328 extern unsigned short REG_RAD4_PA_BIAS_DAC;
00329 extern unsigned short REG_RAD4_RX_GAIN;
00330 extern unsigned short REG_RAD4_TX_VGA_GAIN;
00331 
00332 unsigned int* radio_controller_baseaddr;
00333 
00334 void transmit(int val);
00335 
00336 void transRadio(int ssval, unsigned int val);
00337 
00338 void transmitdac(int val);
00339 
00340 #endif
Updated on Sat Oct 11 00:50:52 2008 WARP