# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
SHARED
|
fpga_0_radio_bridge_slot_2_radio_DIPSW_pin |
I |
0:3 |
fpga_0_radio_bridge_slot_2_radio_DIPSW_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin |
I |
0:7 |
fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin |
I |
1 |
fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin |
I |
1 |
fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin |
I |
1 |
fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin |
I |
1 |
fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_MDIO_0_pin |
IO |
1 |
fpga_0_TriMode_MAC_GMII_MDIO_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin |
O |
0:7 |
fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin |
O |
1 |
fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin |
O |
1 |
fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin |
O |
1 |
fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_MDC_0_pin |
O |
1 |
fpga_0_TriMode_MAC_GMII_MDC_0_pin |
|
TriMode_MAC_GMII
|
fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin |
O |
1 |
fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin |
|
UserIO
|
fpga_0_UserIO_DIPSW_in_pin |
I |
3:0 |
fpga_0_UserIO_DIPSW_in_pin |
|
UserIO
|
fpga_0_UserIO_PB_in_pin |
I |
3:0 |
fpga_0_UserIO_PB_in_pin |
|
UserIO
|
fpga_0_UserIO_IOEx_SCL_pin |
O |
1 |
fpga_0_UserIO_IOEx_SCL_pin |
|
UserIO
|
fpga_0_UserIO_IOEx_SDA_pin |
O |
1 |
fpga_0_UserIO_IOEx_SDA_pin |
|
UserIO
|
fpga_0_UserIO_LEDs_out_pin |
O |
7:0 |
fpga_0_UserIO_LEDs_out_pin |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_A_pin |
I |
0:13 |
fpga_0_analog_bridge_slot_4_analog_ADC_A |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_B_pin |
I |
0:13 |
fpga_0_analog_bridge_slot_4_analog_ADC_B |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin |
I |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_otrA |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin |
I |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_otrB |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_DCS |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_DFS |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin |
O |
0:13 |
fpga_0_analog_bridge_slot_4_analog_DAC1_A |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin |
O |
0:13 |
fpga_0_analog_bridge_slot_4_analog_DAC1_B |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_DAC1_sleep |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin |
O |
0:13 |
fpga_0_analog_bridge_slot_4_analog_DAC2_A |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin |
O |
0:13 |
fpga_0_analog_bridge_slot_4_analog_DAC2_B |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_analog_DAC2_sleep |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_analog_LED_pin |
O |
2:0 |
fpga_0_analog_bridge_slot_4_analog_LED |
|
analog_bridge_slot_4
|
fpga_0_analog_bridge_slot_4_clock_out_pin |
O |
1 |
fpga_0_analog_bridge_slot_4_clock_out |
|
clk_board_config
|
fpga_0_clk_board_config_sys_clk_pin |
I |
1 |
fpga_0_clk_board_config_sys_clk_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_logic_clk_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_logic_clk_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_logic_csb_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_logic_csb_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_logic_dat_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_logic_dat_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_logic_en_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_logic_en_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_radio_clk_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_radio_clk_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_radio_csb_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_radio_csb_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_radio_dat_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_radio_dat_out_pin |
|
clk_board_config
|
fpga_0_clk_board_config_cfg_radio_en_out_pin |
O |
1 |
fpga_0_clk_board_config_cfg_radio_en_out_pin |
|
clock_generator_0
|
fpga_0_clk_1_sys_clk_pin |
I |
1 |
CLK_S |
CLK |
debugOutputs
|
debug_GPIO_d_out_pin |
O |
1:0 |
fpga_0_debug_GPIO_d_out |
|
eeprom_controller
|
fpga_0_eeprom_controller_DQ0_pin |
IO |
1 |
fpga_0_eeprom_controller_DQ0_pin |
|
ofdm_txrx_mimo_plbw_0
|
debug_chipscopetrig_pin |
I |
1 |
debug_chipscopetrig |
|
ofdm_txrx_mimo_plbw_0
|
rx_ext_force_cs_pin |
I |
1 |
rx_ext_force_cs |
|
ofdm_txrx_mimo_plbw_0
|
tx_ext_txstart_pin |
I |
1 |
debug_extTxStart |
|
ofdm_txrx_mimo_plbw_0
|
tx_running_d0_pin |
O |
1 |
tx_running_d0 |
|
proc_sys_reset_0
|
fpga_0_rst_1_sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_ADC_I_pin |
I |
0:13 |
fpga_0_radio_bridge_slot_2_radio_ADC_I_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin |
I |
0:13 |
fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin |
I |
1 |
fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_LD_pin |
I |
1 |
fpga_0_radio_bridge_slot_2_radio_LD_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin |
I |
0:9 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin |
I |
1 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin |
I |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin |
I |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin |
IO |
1 |
fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_converter_clock_out_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_converter_clock_out_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_dac_spi_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_dac_spi_clk_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_dac_spi_cs_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_dac_spi_cs_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_dac_spi_data_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_dac_spi_data_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_24PA_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_24PA_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_5PA_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_5PA_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_ANTSW_pin |
O |
0:1 |
fpga_0_radio_bridge_slot_2_radio_ANTSW_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_B_pin |
O |
0:6 |
fpga_0_radio_bridge_slot_2_radio_B_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_DAC_I_pin |
O |
0:15 |
fpga_0_radio_bridge_slot_2_radio_DAC_I_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin |
O |
0:15 |
fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_LED_pin |
O |
0:2 |
fpga_0_radio_bridge_slot_2_radio_LED_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RxEn_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RxEn_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_RxHP_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_RxHP_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_SHDN_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_SHDN_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_TxEn_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_TxEn_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_spi_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_spi_clk_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_spi_cs_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_spi_cs_pin |
|
radio_bridge_slot_2
|
fpga_0_radio_bridge_slot_2_radio_spi_data_pin |
O |
1 |
fpga_0_radio_bridge_slot_2_radio_spi_data_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_ADC_I_pin |
I |
0:13 |
fpga_0_radio_bridge_slot_3_radio_ADC_I_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin |
I |
0:13 |
fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin |
I |
1 |
fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_DIPSW_pin |
I |
0:3 |
fpga_0_radio_bridge_slot_3_radio_DIPSW_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_LD_pin |
I |
1 |
fpga_0_radio_bridge_slot_3_radio_LD_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin |
I |
0:9 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin |
I |
1 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin |
I |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin |
I |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin |
IO |
1 |
fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_converter_clock_out_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_converter_clock_out_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_dac_spi_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_dac_spi_clk_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_dac_spi_cs_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_dac_spi_cs_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_dac_spi_data_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_dac_spi_data_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_24PA_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_24PA_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_5PA_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_5PA_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_ANTSW_pin |
O |
0:1 |
fpga_0_radio_bridge_slot_3_radio_ANTSW_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_B_pin |
O |
0:6 |
fpga_0_radio_bridge_slot_3_radio_B_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_DAC_I_pin |
O |
0:15 |
fpga_0_radio_bridge_slot_3_radio_DAC_I_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin |
O |
0:15 |
fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_LED_pin |
O |
0:2 |
fpga_0_radio_bridge_slot_3_radio_LED_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RxEn_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RxEn_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_RxHP_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_RxHP_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_SHDN_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_SHDN_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_TxEn_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_TxEn_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_spi_clk_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_spi_clk_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_spi_cs_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_spi_cs_pin |
|
radio_bridge_slot_3
|
fpga_0_radio_bridge_slot_3_radio_spi_data_pin |
O |
1 |
fpga_0_radio_bridge_slot_3_radio_spi_data_pin |
|
rs232_db9
|
fpga_0_rs232_db9_RX_pin |
I |
1 |
fpga_0_rs232_db9_RX_pin |
|
rs232_db9
|
fpga_0_rs232_db9_TX_pin |
O |
1 |
fpga_0_rs232_db9_TX_pin |
|
rs232_usb
|
fpga_0_rs232_usb_RX_pin |
I |
1 |
fpga_0_rs232_usb_RX_pin |
|
rs232_usb
|
fpga_0_rs232_usb_TX_pin |
O |
1 |
fpga_0_rs232_usb_TX_pin |
|
Unconnected
|
debug |
O |
6:0 |
debug_tx_pktrunning & debug_rx_payload & debug_pktDetOut & rx_int_goodpkt & rx_int_badpkt & rx_int_goodheader & ofdm_txrx_mimo_plbw_0_rx_int_badheader |
|
Unconnected
|
rx_ext_pktdet_in1_pin |
I |
1 |
rx_extpktdet_in1 |
|
Unconnected
|
rx_ext_pktdet_in2_pin |
I |
1 |
rx_extpktdet_in2 |
|