Overview
Block Diagram
External Ports
 Processor
   ppc405_0
 Busses
   plb
   plb_32b_40MHz
   ppc405_0_docm
   ppc405_0_iocm
 Bridge
   plbv46_plbv46_bridge_0
 Memorys
   plb_bram_if_cntlr_1_bram
   plb_bram_if_cntlr_2_bram
   ppc405_0_docm_cntlr_bram
   ppc405_0_iocm_cntlr_bram
 Memory Controllers
   ppc405_0_docm_cntlr
   ppc405_0_iocm_cntlr
   xps_bram_if_cntlr_1
   xps_bram_if_cntlr_2
 Peripherals
   TriMode_MAC_GMII
   TriMode_MAC_GMII_fifo
   UserIO
   debugOutputs
   eeprom_controller
   jtagppc_cntlr_inst
   ofdm_agc_mimo_plbw_0
   ofdm_txrx_mimo_plbw_0
   proc_sys_reset_0
   radio_bridge_slot_2
   radio_bridge_slot_3
   radio_controller_0
   rate_change_filters_plbw_0
   rs232_db9
   rs232_usb
   warp_timer_plbw_0
   xps_central_dma_0
 IP
   analog_bridge_slot_4
   clk_board_config
   clock_generator_0
   util_bus_split_0
   util_reduced_logic_0
   util_reduced_logic_1
   util_reduced_logic_2
Timing Information