TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processor
   ppc405_0
Busses
   plb
   plb_32b_40MHz
   ppc405_0_docm
   ppc405_0_iocm
Memory
   plb_bram_if_cntlr_1_bram
   plb_bram_if_cntlr_2_bram
   ppc405_0_docm_cntlr_bram
   ppc405_0_iocm_cntlr_bram
Memory Controllers
   ppc405_0_docm_cntlr
   ppc405_0_iocm_cntlr
   xps_bram_if_cntlr_1
   xps_bram_if_cntlr_2
Peripherals
   TriMode_MAC_GMII
   TriMode_MAC_GMII_fifo
   UserIO
   debugOutputs
   eeprom_controller
   jtagppc_cntlr_inst
   ofdm_agc_mimo_plbw_0
   ofdm_txrx_mimo_plbw_0
   proc_sys_reset_0
   radio_bridge_slot_2
   radio_bridge_slot_3
   radio_controller_0
   rate_change_filters_plbw_0
   rs232_db9
   rs232_usb
   warp_timer_plbw_0
   xps_central_dma_0
IP
   analog_bridge_slot_4
   clk_board_config
   clock_generator_0
   util_bus_split_0
   util_reduced_logic_0
   util_reduced_logic_1
   util_reduced_logic_2
Timing Information
Overview TOC
Resources Used
1   PowerPC 405 Virtex-4
1   Instruction-Side On-Chip Memory (OCM) Bus 1.0
1   Data-Side On-Chip Memory (OCM) Bus 1.0
2   Processor Local Bus (PLB) 4.6
1   PLBV46 to PLBV46 Bridge
4   Block RAM (BRAM) Block
2   XPS BRAM Controller
1   Instruction-Side OCM BRAM Controller
1   Data-Side OCM BRAM Controller
1   XPS Central DMA Controller
3   Utility Reduced Logic
1   Utility Bus Split
2   XPS UART (Lite)
1   WARP Radio Controller (PLB46)
2   WARP Radio Board Bridge Core
1   Processor System Reset Module
1   PowerPC JTAG Controller
1   EEPROM Controller based on Maxim OneWire Master core
1   XPS General Purpose IO
1   Clock Generator
1   WARP Clock Board Configuration Core
1   XPS LocalLink FIFO
1   XPS LocalLink Tri-mode Ethernet MAC
Specifics
Generated Wed May 02 23:00:42 2012
EDK Version 13.4
Device Family virtex4
Device xc4vfx100ff1517-11

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin I 0:7 fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MDIO_0_pin IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin O 0:7 fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MDC_0_pin O 1 fpga_0_TriMode_MAC_GMII_MDC_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
UserIO fpga_0_UserIO_DIPSW_in_pin I 3:0 fpga_0_UserIO_DIPSW_in_pin
UserIO fpga_0_UserIO_PB_in_pin I 3:0 fpga_0_UserIO_PB_in_pin
UserIO fpga_0_UserIO_IOEx_SCL_pin O 1 fpga_0_UserIO_IOEx_SCL_pin
UserIO fpga_0_UserIO_IOEx_SDA_pin O 1 fpga_0_UserIO_IOEx_SDA_pin
UserIO fpga_0_UserIO_LEDs_out_pin O 7:0 fpga_0_UserIO_LEDs_out_pin
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_A_pin I 0:13 fpga_0_analog_bridge_slot_4_analog_ADC_A
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_B_pin I 0:13 fpga_0_analog_bridge_slot_4_analog_ADC_B
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC1_A
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC1_B
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC2_A
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC2_B
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_analog_LED_pin O 2:0 fpga_0_analog_bridge_slot_4_analog_LED
analog_bridge_slot_4 fpga_0_analog_bridge_slot_4_clock_out_pin O 1 fpga_0_analog_bridge_slot_4_clock_out
clk_board_config fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 CLK_S  CLK 
debugOutputs debug_GPIO_d_out_pin O 1:0 fpga_0_debug_GPIO_d_out
eeprom_controller fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0_pin
ofdm_txrx_mimo_plbw_0 debug_chipscopetrig_pin I 1 debug_chipscopetrig
ofdm_txrx_mimo_plbw_0 rx_ext_force_cs_pin I 1 rx_ext_force_cs
ofdm_txrx_mimo_plbw_0 tx_ext_txstart_pin I 1 debug_extTxStart
ofdm_txrx_mimo_plbw_0 tx_running_d0_pin O 1 tx_running_d0
proc_sys_reset_0 fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_2_radio_B_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_2_radio_LED_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_3_radio_B_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_3_radio_LED_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data_pin
rs232_db9 fpga_0_rs232_db9_RX_pin I 1 fpga_0_rs232_db9_RX_pin
rs232_db9 fpga_0_rs232_db9_TX_pin O 1 fpga_0_rs232_db9_TX_pin
rs232_usb fpga_0_rs232_usb_RX_pin I 1 fpga_0_rs232_usb_RX_pin
rs232_usb fpga_0_rs232_usb_TX_pin O 1 fpga_0_rs232_usb_TX_pin
Unconnected debug O 6:0 debug_tx_pktrunning & debug_rx_payload & debug_pktDetOut & rx_int_goodpkt & rx_int_badpkt & rx_int_goodheader & ofdm_txrx_mimo_plbw_0_rx_int_badheader
Unconnected rx_ext_pktdet_in1_pin I 1 rx_extpktdet_in1
Unconnected rx_ext_pktdet_in2_pin I 1 rx_extpktdet_in2


Processors TOC

ppc405_0   PowerPC 405 Virtex-4
A wrapper to instantiate the PowerPC 405 Processor Block primitive

IP Specs
Core Version Documentation
ppc405_virtex4 2.01.b IP


ppc405_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CPMC405CLOCK I 1 clk_160_0000MHzDCM0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DPLB0 MASTER PLBV46 plb 12 Peripherals.
IPLB0 MASTER PLBV46 plb 12 Peripherals.
DSOCM MASTER DSOCM ppc405_0_docm ppc405_0_docm_cntlr
ISOCM MASTER ISOCM ppc405_0_iocm ppc405_0_iocm_cntlr
JTAGPPC TARGET XIL_JTAGPPC ppc405_0_jtagppc_bus jtagppc_cntlr_inst
RESETPPC TARGET XIL_RESETPPC ppc_reset_bus proc_sys_reset_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DPLB0_DWIDTH 64
C_DPLB0_NATIVE_DWIDTH 64
C_IPLB0_DWIDTH 64
C_IPLB0_NATIVE_DWIDTH 64
C_DPLB1_DWIDTH 64
C_DPLB1_NATIVE_DWIDTH 64
C_IPLB1_DWIDTH 64
C_IPLB1_NATIVE_DWIDTH 64
C_DPLB1_ADDR_BASE 0xFFFFFFFF
C_DPLB1_ADDR_HIGH 0x00000000
C_IPLB1_ADDR_BASE 0xFFFFFFFF
C_IPLB1_ADDR_HIGH 0x00000000
C_FASTEST_PLB_CLOCK DPLB0
C_GENERATE_PLB_TIMESPECS 1
C_DPLB0_P2P 1
C_DPLB1_P2P 1
C_IPLB0_P2P 1
C_IPLB1_P2P 1
 
Name Value
C_IDCR_BASEADDR 0B0100000000
C_IDCR_HIGHADDR 0B0111111111
C_DISABLE_OPERAND_FORWARDING 1
C_MMU_ENABLE 1
C_DETERMINISTIC_MULT 0
C_PLBSYNCBYPASS 1
C_APU_CONTROL 0B1101111000000000
C_APU_UDI_1 0B101000011000100110000011
C_APU_UDI_2 0B101000111000100110000011
C_APU_UDI_3 0B101001011000100111000011
C_APU_UDI_4 0B101001111000100111000011
C_APU_UDI_5 0B101010011000110000000011
C_APU_UDI_6 0B101010111000110000000011
C_APU_UDI_7 0B101011011000110001000011
C_APU_UDI_8 0B101011111000110001000011
C_PVR_HIGH 0B0000
C_PVR_LOW 0B0000
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOC

plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.05.a IP


plb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
xps_central_dma_0 MASTER MPLB
ppc405_0 MASTER DPLB0
ppc405_0 MASTER IPLB0
xps_central_dma_0 SLAVE SPLB
xps_bram_if_cntlr_2 SLAVE SPLB
xps_bram_if_cntlr_1 SLAVE SPLB
warp_timer_plbw_0 SLAVE SPLB
rs232_usb SLAVE SPLB
rs232_db9 SLAVE SPLB
rate_change_filters_plbw_0 SLAVE SPLB
plbv46_plbv46_bridge_0 SLAVE SPLB
debugOutputs SLAVE SPLB
UserIO SLAVE SPLB
TriMode_MAC_GMII_fifo SLAVE SPLB
TriMode_MAC_GMII SLAVE SPLB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0B1111111111
C_HIGHADDR 0B0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 100
C_ADDR_PIPELINING_TYPE 1
C_FAMILY virtex5
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


plb_32b_40MHz   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.05.a IP


plb_32b_40MHz IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_40_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
plbv46_plbv46_bridge_0 MASTER MPLB
radio_controller_0 SLAVE SPLB
ofdm_txrx_mimo_plbw_0 SLAVE SPLB
ofdm_agc_mimo_plbw_0 SLAVE SPLB
eeprom_controller SLAVE SPLB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0B1111111111
C_HIGHADDR 0B0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 100
C_ADDR_PIPELINING_TYPE 1
C_FAMILY virtex5
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_docm   Data-Side On-Chip Memory (OCM) Bus 1.0
Data-Side On-Chip Memory(OCM) bus interconnect core

IP Specs
Core Version Documentation
dsocm_v10 2.00.b IP


ppc405_0_docm IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 DSOCM_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
ppc405_0 MASTER DSOCM
ppc405_0_docm_cntlr SLAVE DSOCM


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_MASTERS 1
C_NUM_SLAVES 1
C_DSCNTLVALUE 0xA3
C_DSARCVALUE 0x31
C_FIXED_LATENCY 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm   Instruction-Side On-Chip Memory (OCM) Bus 1.0
Instruction-side On-Chip Memory(OCM) bus interconnect core

IP Specs
Core Version Documentation
isocm_v10 2.00.b IP


ppc405_0_iocm IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 ISOCM_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
ppc405_0 MASTER ISOCM
ppc405_0_iocm_cntlr SLAVE ISOCM


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_MASTERS 1
C_NUM_SLAVES 1
C_ISCNTLVALUE 0xA3
C_ISARCVALUE 0x30
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Bridges TOC

plbv46_plbv46_bridge_0   PLBV46 to PLBV46 Bridge
PLBV46 to PLBV46 bridge.

IP Specs
Core Version Documentation
plbv46_plbv46_bridge 1.04.a IP


plbv46_plbv46_bridge_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MPLB MASTER PLBV46 plb_32b_40MHz 4 Peripherals.
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_ADDR_RNG 4
C_BRIDGE_BASEADDR 0x86200000
C_BRIDGE_HIGHADDR 0x8620FFFF
C_RNG0_BASEADDR 0xC4000000
C_RNG0_HIGHADDR 0xC400FFFF
C_RNG1_BASEADDR 0xC5400000
C_RNG1_HIGHADDR 0xC540FFFF
C_RNG2_BASEADDR 0xCAC00000
C_RNG2_HIGHADDR 0xCAC0FFFF
C_RNG3_BASEADDR 0xCDA00000
C_RNG3_HIGHADDR 0xCDA0FFFF
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SMALLEST_MASTER 32
C_SPLB_BIGGEST_MASTER 32
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_MPLB_AWIDTH 32
C_MPLB_DWIDTH 32
C_SPLB_NATIVE_DWIDTH 32
C_MPLB_NATIVE_DWIDTH 32
C_MPLB_SMALLEST_SLAVE 32
C_BUS_CLOCK_RATIO 2
C_PREFETCH_TIMEOUT 10
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOC

plb_bram_if_cntlr_1_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


plb_bram_if_cntlr_1_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM xps_bram_if_cntlr_1_port xps_bram_if_cntlr_1


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


plb_bram_if_cntlr_2_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


plb_bram_if_cntlr_2_bram IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 BRAM_Clk_B I 1 clk_40_0000MHz
1 BRAM_EN_B I 1 net_vcc
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM xps_bram_if_cntlr_2_port xps_bram_if_cntlr_2
PORTB TARGET XIL_BRAM ofdm_txrx_mimo_plbw_0_PORTB ofdm_txrx_mimo_plbw_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_docm_cntlr_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


ppc405_0_docm_cntlr_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ppc405_0_docm_cntlr_porta ppc405_0_docm_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm_cntlr_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


ppc405_0_iocm_cntlr_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ppc405_0_iocm_cntlr_porta ppc405_0_iocm_cntlr
PORTB TARGET XIL_BRAM ppc405_0_iocm_cntlr_portb ppc405_0_iocm_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOC

ppc405_0_docm_cntlr   Data-Side OCM BRAM Controller
BRAM_Block connects to the DSOCM V10 Bus for Virtex-II Pro PowerPC 405 based embedded systems.

IP Specs
Core Version Documentation
dsbram_if_cntlr 3.00.c IP


ppc405_0_docm_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA INITIATOR XIL_BRAM ppc405_0_docm_cntlr_porta ppc405_0_docm_cntlr_bram
DSOCM SLAVE DSOCM ppc405_0_docm ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x40110000
C_HIGHADDR 0x4011FFFF
C_BRAM_EN 0
C_RANGECHECK 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm_cntlr   Instruction-Side OCM BRAM Controller
BRAM_Block connects to the ISOCM V10 Bus for Virtex-II Pro PowerPC 405 based embedded systems.

IP Specs
Core Version Documentation
isbram_if_cntlr 3.00.c IP


ppc405_0_iocm_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DCR_WRITE_PORT INITIATOR XIL_BRAM ppc405_0_iocm_cntlr_porta ppc405_0_iocm_cntlr_bram
INSTRN_READ_PORT INITIATOR XIL_BRAM ppc405_0_iocm_cntlr_portb ppc405_0_iocm_cntlr_bram
ISOCM SLAVE ISOCM ppc405_0_iocm ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000FFFF
C_BRAM_EN 0
C_RANGECHECK 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_bram_if_cntlr_1   XPS BRAM Controller
Attaches BRAM to the PLBV46

IP Specs
Core Version Documentation
xps_bram_if_cntlr 1.00.b IP


xps_bram_if_cntlr_1 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA INITIATOR XIL_BRAM xps_bram_if_cntlr_1_port plb_bram_if_cntlr_1_bram
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xFFFF0000
C_HIGHADDR 0xFFFFFFFF
C_SPLB_NATIVE_DWIDTH 64
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_NUM_MASTERS 2
 
Name Value
C_SPLB_MID_WIDTH 1
C_SPLB_SUPPORT_BURSTS 1
C_SPLB_P2P 0
C_SPLB_SMALLEST_MASTER 32
C_FAMILY virtex5
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_bram_if_cntlr_2   XPS BRAM Controller
Attaches BRAM to the PLBV46

IP Specs
Core Version Documentation
xps_bram_if_cntlr 1.00.b IP


xps_bram_if_cntlr_2 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA INITIATOR XIL_BRAM xps_bram_if_cntlr_2_port plb_bram_if_cntlr_2_bram
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00010000
C_HIGHADDR 0x0001FFFF
C_SPLB_NATIVE_DWIDTH 64
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_NUM_MASTERS 2
 
Name Value
C_SPLB_MID_WIDTH 1
C_SPLB_SUPPORT_BURSTS 1
C_SPLB_P2P 0
C_SPLB_SMALLEST_MASTER 32
C_FAMILY virtex5
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOC

TriMode_MAC_GMII   XPS LocalLink Tri-mode Ethernet MAC


IP Specs
Core Version Documentation
xps_ll_temac 2.03.a IP


TriMode_MAC_GMII IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 TemacPhy_RST_n O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
1 GTX_CLK_0 I 1 clk_125_0000MHz
2 REFCLK I 1 clk_200_0000MHz
3 LlinkTemac0_CLK I 1 clk_80_0000MHzDCM0
4 MII_TX_CLK_0 I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
5 GMII_TXD_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
6 GMII_TX_EN_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
7 GMII_TX_ER_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
8 GMII_TX_CLK_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
9 GMII_RXD_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
10 GMII_RX_DV_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
11 GMII_RX_ER_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
12 GMII_RX_CLK_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
13 MDC_0 O 1 fpga_0_TriMode_MAC_GMII_MDC_0_pin
14 MDIO_0 IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
LLINK0 INITIATOR XIL_LL_DMA TriMode_MAC_GMII_llink0 TriMode_MAC_GMII_fifo
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_IDELAYCTRL 2
C_IDELAYCTRL_LOC IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
C_SUBFAMILY FX
C_RESERVED 0
C_SPLB_NATIVE_DWIDTH 32
C_FAMILY virtex5
C_BASEADDR 0x87000000
C_HIGHADDR 0x8707FFFF
C_SPLB_DWIDTH 32
C_SPLB_AWIDTH 32
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
C_SPLB_P2P 0
C_INCLUDE_IO 1
C_PHY_TYPE 1
C_TEMAC1_ENABLED 0
C_TEMAC0_TXFIFO 4096
C_TEMAC0_RXFIFO 4096
C_TEMAC1_TXFIFO 4096
C_TEMAC1_RXFIFO 4096
C_BUS2CORE_CLK_RATIO 1
C_TEMAC_TYPE 1
C_TEMAC0_TXCSUM 0
C_TEMAC0_RXCSUM 0
 
Name Value
C_TEMAC1_TXCSUM 0
C_TEMAC1_RXCSUM 0
C_TEMAC0_PHYADDR 0B00001
C_TEMAC1_PHYADDR 0B00010
C_TEMAC0_TXVLAN_TRAN 0
C_TEMAC0_RXVLAN_TRAN 0
C_TEMAC1_TXVLAN_TRAN 0
C_TEMAC1_RXVLAN_TRAN 0
C_TEMAC0_TXVLAN_TAG 0
C_TEMAC0_RXVLAN_TAG 0
C_TEMAC1_TXVLAN_TAG 0
C_TEMAC1_RXVLAN_TAG 0
C_TEMAC0_TXVLAN_STRP 0
C_TEMAC0_RXVLAN_STRP 0
C_TEMAC1_TXVLAN_STRP 0
C_TEMAC1_RXVLAN_STRP 0
C_TEMAC0_MCAST_EXTEND 0
C_TEMAC1_MCAST_EXTEND 0
C_TEMAC0_STATS 0
C_TEMAC1_STATS 0
C_TEMAC0_AVB 0
C_TEMAC1_AVB 0
C_SIMULATION 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


TriMode_MAC_GMII_fifo   XPS LocalLink FIFO


IP Specs
Core Version Documentation
xps_ll_fifo 1.02.a IP


TriMode_MAC_GMII_fifo IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.
LLINK TARGET XIL_LL_DMA TriMode_MAC_GMII_llink0 TriMode_MAC_GMII


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SPLB_MID_WIDTH 3
C_SPLB_NUM_MASTERS 8
C_SPLB_SMALLEST_MASTER 128
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_AWIDTH 32
C_BASEADDR 0x81A00000
C_HIGHADDR 0x81A0FFFF
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


UserIO


IP Specs
Core Version
warp_v4_userio 1.00.a


UserIO IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 LEDs_out O 1 fpga_0_UserIO_LEDs_out_pin
1 IOEx_SDA O 1 fpga_0_UserIO_IOEx_SDA_pin
2 IOEx_SCL O 1 fpga_0_UserIO_IOEx_SCL_pin
3 PB_in I 1 fpga_0_UserIO_PB_in_pin
4 DIPSW_in I 1 fpga_0_UserIO_DIPSW_in_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ADDRESS_0 0x40
C_ADDRESS_1 0x42
C_I2C_DIVIDER 0x40
C_BASEADDR 0xC9600000
C_HIGHADDR 0xC960FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
 
Name Value
C_SPLB_MID_WIDTH 3
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_INCLUDE_DPHASE_TIMER 0
C_FAMILY virtex4
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


debugOutputs   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


debugOutputs IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_O O 1 fpga_0_debug_GPIO_d_out
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81400000
C_HIGHADDR 0x8140FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY virtex5
 
Name Value
C_ALL_INPUTS 0
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 2
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


eeprom_controller   EEPROM Controller based on Maxim OneWire Master core


IP Specs
Core Version
eeprom_onewire 1.10.a


eeprom_controller IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 DQ0 IO 1 fpga_0_eeprom_controller_DQ0_pin
1 DQ2_T O 1 radio_bridge_slot_2_user_EEPROM_IO_T
2 DQ2_O O 1 radio_bridge_slot_2_user_EEPROM_IO_O
3 DQ2_I I 1 radio_bridge_slot_2_user_EEPROM_IO_I
4 DQ3_T O 1 radio_bridge_slot_3_user_EEPROM_IO_T
5 DQ3_O O 1 radio_bridge_slot_3_user_EEPROM_IO_O
6 DQ3_I I 1 radio_bridge_slot_3_user_EEPROM_IO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb_32b_40MHz 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
 
Name Value
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_INCLUDE_DPHASE_TIMER 0
C_FAMILY virtex5
C_MEM0_BASEADDR 0xC5400000
C_MEM0_HIGHADDR 0xC540FFFF
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


jtagppc_cntlr_inst   PowerPC JTAG Controller
JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA.

IP Specs
Core Version Documentation
jtagppc_cntlr 2.01.c IP


jtagppc_cntlr_inst IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
JTAGPPC0 INITIATOR XIL_JTAGPPC ppc405_0_jtagppc_bus ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DEVICE X2VP4
C_NUM_PPC_USED 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ofdm_agc_mimo_plbw_0


IP Specs
Core Version
ofdm_agc_mimo_plbw 2.00.a


ofdm_agc_mimo_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 i_in_a I 1 radio_bridge_slot_2_user_ADC_I_filt
1 q_in_a I 1 radio_bridge_slot_2_user_ADC_Q_filt
2 i_in_b I 1 radio_bridge_slot_3_user_ADC_I_filt
3 q_in_b I 1 radio_bridge_slot_3_user_ADC_Q_filt
4 i_out_a O 1 ofdmRx_antA_ADC_I
5 q_out_a O 1 ofdmRx_antA_ADC_Q
6 i_out_b O 1 ofdmRx_antB_ADC_I
7 q_out_b O 1 ofdmRx_antB_ADC_Q
8 packet_in I 1 phy_pktdet
9 rssi_in_a I 1 radio_bridge_slot_2_user_RSSI_ADC_D
10 rssi_in_b I 1 radio_bridge_slot_3_user_RSSI_ADC_D
11 rxhp_a O 1 agc_rxhp_a
12 rxhp_b O 1 agc_rxhp_b
13 g_bb_a O 1 agc_g_bb_a
14 g_rf_a O 1 agc_g_rf_a
15 g_bb_b O 1 agc_g_bb_b
16 g_rf_b O 1 agc_g_rf_b
17 reset_in I 1 rx_pktdetreset
18 done_a O 1 agc_done_a
19 done_b O 1 agc_done_b
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb_32b_40MHz 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xC4000000
C_HIGHADDR 0xC400FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_MEMMAP_GRF_A 0x800
C_MEMMAP_GRF_A_N_BITS 2
C_MEMMAP_GRF_A_BIN_PT 0
C_MEMMAP_GRF_B 0x804
C_MEMMAP_GRF_B_N_BITS 2
C_MEMMAP_GRF_B_BIN_PT 0
C_MEMMAP_GBB_B 0x808
C_MEMMAP_GBB_B_N_BITS 5
C_MEMMAP_GBB_B_BIN_PT 0
C_MEMMAP_GBB_A 0x80C
C_MEMMAP_GBB_A_N_BITS 5
C_MEMMAP_GBB_A_BIN_PT 0
C_MEMMAP_BITS_R 0x810
C_MEMMAP_BITS_R_N_BITS 10
C_MEMMAP_BITS_R_BIN_PT 0
C_MEMMAP_BITS_W 0x800
C_MEMMAP_BITS_W_N_BITS 10
C_MEMMAP_BITS_W_BIN_PT 0
C_MEMMAP_GBB_INIT 0x804
C_MEMMAP_GBB_INIT_N_BITS 16
C_MEMMAP_GBB_INIT_BIN_PT 0
C_MEMMAP_ADJ 0x808
C_MEMMAP_ADJ_N_BITS 16
 
Name Value
C_MEMMAP_ADJ_BIN_PT 0
C_MEMMAP_DCO_IIR_COEF_FB 0x80C
C_MEMMAP_DCO_IIR_COEF_FB_N_BITS 18
C_MEMMAP_DCO_IIR_COEF_FB_BIN_PT 17
C_MEMMAP_THRESHOLDS 0x810
C_MEMMAP_THRESHOLDS_N_BITS 32
C_MEMMAP_THRESHOLDS_BIN_PT 0
C_MEMMAP_TIMING 0x814
C_MEMMAP_TIMING_N_BITS 32
C_MEMMAP_TIMING_BIN_PT 0
C_MEMMAP_DCO_IIR_COEF_GAIN 0x818
C_MEMMAP_DCO_IIR_COEF_GAIN_N_BITS 18
C_MEMMAP_DCO_IIR_COEF_GAIN_BIN_PT 17
C_MEMMAP_AVG_LEN 0x81C
C_MEMMAP_AVG_LEN_N_BITS 16
C_MEMMAP_AVG_LEN_BIN_PT 0
C_MEMMAP_AGC_EN 0x820
C_MEMMAP_AGC_EN_N_BITS 1
C_MEMMAP_AGC_EN_BIN_PT 0
C_MEMMAP_DCO_TIMING 0x824
C_MEMMAP_DCO_TIMING_N_BITS 32
C_MEMMAP_DCO_TIMING_BIN_PT 0
C_MEMMAP_T_DB 0x828
C_MEMMAP_T_DB_N_BITS 16
C_MEMMAP_T_DB_BIN_PT 0
C_MEMMAP_MRESET_IN 0x82C
C_MEMMAP_MRESET_IN_N_BITS 1
C_MEMMAP_MRESET_IN_BIN_PT 0
C_MEMMAP_SRESET_IN 0x830
C_MEMMAP_SRESET_IN_N_BITS 1
C_MEMMAP_SRESET_IN_BIN_PT 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ofdm_txrx_mimo_plbw_0


IP Specs
Core Version
ofdm_txrx_supermimo_coded_plbw 4.00.c


ofdm_txrx_mimo_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 rx_anta_adci I 1 ofdmRx_antA_ADC_I
1 rx_anta_adcq I 1 ofdmRx_antA_ADC_Q
2 rx_antb_adci I 1 ofdmRx_antB_ADC_I
3 rx_antb_adcq I 1 ofdmRx_antB_ADC_Q
4 rx_reset I 1 sys_periph_reset
5 tx_reset I 1 sys_periph_reset
6 tx_starttransmit I 1 txPHYStart
7 rx_int_badpkt O 1 rx_int_badpkt
8 rx_int_goodpkt O 1 rx_int_goodpkt
9 rx_int_goodheader O 1 rx_int_goodheader
10 tx_pktdone O 1 tx_pktdone
11 rx_pktdetreset O 1 rx_pktdetreset
12 tx_anta_dac_i O 1 radio_bridge_slot_2_user_DAC_I
13 tx_anta_dac_q O 1 radio_bridge_slot_2_user_DAC_Q
14 tx_antb_dac_i O 1 radio_bridge_slot_3_user_DAC_I
15 tx_antb_dac_q O 1 radio_bridge_slot_3_user_DAC_Q
16 tx_anta_i_div1 I 1 ofdmtx_postfilt_anta_i
17 tx_anta_q_div1 I 1 ofdmtx_postfilt_anta_q
18 tx_antb_i_div1 I 1 ofdmtx_postfilt_antb_i
19 tx_antb_q_div1 I 1 ofdmtx_postfilt_antb_q
20 tx_anta_i_div4 O 1 ofdmtx_prefilt_anta_i
21 tx_anta_q_div4 O 1 ofdmtx_prefilt_anta_q
22 tx_antb_i_div4 O 1 ofdmtx_prefilt_antb_i
23 tx_antb_q_div4 O 1 ofdmtx_prefilt_antb_q
24 tx_debug_pktrunning O 1 debug_tx_pktrunning
25 debug_chipscopetrig1 I 1 debug_chipscopetrig
26 rx_debug_payload O 1 debug_rx_payload
27 rx_debug_pktdone O 1 debug_rx_pktdone
28 rx_debug_eq_i O 1 ofdm_rx_debug_eq_i
29 rx_debug_eq_q O 1 ofdm_rx_debug_eq_q
30 rx_debug_phasecorrect O 1 rx_debug_phasecorrect
31 rx_debug_phaseerror O 1 rx_debug_phaseerr
32 rx_anta_agc_done I 1 agc_done_a
33 rx_anta_gainbb I 1 agc_g_bb_a
34 rx_anta_gainrf I 1 agc_g_rf_a
35 rx_antb_agc_done I 1 agc_done_b
36 rx_antb_gainbb I 1 agc_g_bb_b
37 rx_antb_gainrf I 1 agc_g_rf_b
38 rx_debug_antsel O 1 debug_antSel
39 rx_int_badheader O 1 ofdm_txrx_mimo_plbw_0_rx_int_badheader
40 rssi_anta I 1 radio_bridge_slot_2_user_RSSI_ADC_D
41 rssi_antb I 1 radio_bridge_slot_3_user_RSSI_ADC_D
42 rssi_clk_out O 1 rssi_pkt_detect_plbw_0_rssi_clk_out
43 idlefordifs O 1 ofdm_pktDetector_mimo_plbw_0_idlefordifs
44 radio_txen O 1 ofdm_txen
45 radio_rxen O 1 ofdm_rxen
46 ext_txen I 1 debug_extTxStart
47 rx_pktdetreset_in I 1 net_gnd
48 ext_pktdet I 1 rx_extpktdet
49 tx_pktrunning_d0 O 1 tx_running_d0
50 tx_pktrunning_d1 O 1 tx_running_d1
51 idlefordifs_disable I 1 rx_ext_force_cs
52 debug_pktDetAutoCorr O 1 debug_pktDetAutoCorr
53 debug_pktDetRSSI O 1 debug_pktDetRSSI
54 pktdet O 1 phy_pktdet
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTB INITIATOR XIL_BRAM ofdm_txrx_mimo_plbw_0_PORTB plb_bram_if_cntlr_2_bram
SPLB SLAVE PLBV46 plb_32b_40MHz 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xCDA00000
C_HIGHADDR 0xCDA0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_MEMMAP_MIDPACKETRSSI 0x80A4
C_MEMMAP_MIDPACKETRSSI_N_BITS 32
C_MEMMAP_MIDPACKETRSSI_BIN_PT 0
C_MEMMAP_TX_PKTRUNNING 0x80A8
C_MEMMAP_TX_PKTRUNNING_N_BITS 32
C_MEMMAP_TX_PKTRUNNING_BIN_PT 0
C_MEMMAP_RX_PKTDETEVENTCOUNT 0x80AC
C_MEMMAP_RX_PKTDETEVENTCOUNT_N_BITS 32
C_MEMMAP_RX_PKTDETEVENTCOUNT_BIN_PT 0
C_MEMMAP_RX_COARSECFOEST 0x80B0
C_MEMMAP_RX_COARSECFOEST_N_BITS 32
C_MEMMAP_RX_COARSECFOEST_BIN_PT 0
C_MEMMAP_RX_PILOTCFOEST 0x80B4
C_MEMMAP_RX_PILOTCFOEST_N_BITS 32
C_MEMMAP_RX_PILOTCFOEST_BIN_PT 0
C_MEMMAP_RX_PKTDONE_INTERRUPTSTATUS 0x80B8
C_MEMMAP_RX_PKTDONE_INTERRUPTSTATUS_N_BITS 32
C_MEMMAP_RX_PKTDONE_INTERRUPTSTATUS_BIN_PT 0
C_MEMMAP_RX_BER_TOTALBITS 0x80BC
C_MEMMAP_RX_BER_TOTALBITS_N_BITS 32
C_MEMMAP_RX_BER_TOTALBITS_BIN_PT 0
C_MEMMAP_RX_BER_ERRORS 0x80C0
C_MEMMAP_RX_BER_ERRORS_N_BITS 32
C_MEMMAP_RX_BER_ERRORS_BIN_PT 0
C_MEMMAP_RX_GAINS 0x80C4
C_MEMMAP_RX_GAINS_N_BITS 32
C_MEMMAP_RX_GAINS_BIN_PT 0
C_MEMMAP_PKTDET_STATUS 0x80C8
C_MEMMAP_PKTDET_STATUS_N_BITS 14
C_MEMMAP_PKTDET_STATUS_BIN_PT 0
C_MEMMAP_FEC_CONFIG 0x8000
C_MEMMAP_FEC_CONFIG_N_BITS 32
C_MEMMAP_FEC_CONFIG_BIN_PT 0
C_MEMMAP_TX_OFDM_SYMCOUNTS 0x8004
C_MEMMAP_TX_OFDM_SYMCOUNTS_N_BITS 32
C_MEMMAP_TX_OFDM_SYMCOUNTS_BIN_PT 0
C_MEMMAP_RX_OFDM_SYMBOLCOUNTS 0x8008
C_MEMMAP_RX_OFDM_SYMBOLCOUNTS_N_BITS 32
C_MEMMAP_RX_OFDM_SYMBOLCOUNTS_BIN_PT 0
C_MEMMAP_TXRX_PILOTS_VALUES 0x800C
C_MEMMAP_TXRX_PILOTS_VALUES_N_BITS 32
C_MEMMAP_TXRX_PILOTS_VALUES_BIN_PT 0
C_MEMMAP_TXRX_PILOTS_INDEX 0x8010
C_MEMMAP_TXRX_PILOTS_INDEX_N_BITS 32
C_MEMMAP_TXRX_PILOTS_INDEX_BIN_PT 0
C_MEMMAP_TXRX_INTERRUPT_PKTBUF_CTRL 0x8014
C_MEMMAP_TXRX_INTERRUPT_PKTBUF_CTRL_N_BITS 32
C_MEMMAP_TXRX_INTERRUPT_PKTBUF_CTRL_BIN_PT 0
C_MEMMAP_TXRX_FFT_SCALING 0x8018
C_MEMMAP_TXRX_FFT_SCALING_N_BITS 12
C_MEMMAP_TXRX_FFT_SCALING_BIN_PT 0
C_MEMMAP_TX_START_RESET_CONTROL 0x801C
C_MEMMAP_TX_START_RESET_CONTROL_N_BITS 32
C_MEMMAP_TX_START_RESET_CONTROL_BIN_PT 0
C_MEMMAP_TX_CONTROLBITS 0x8020
C_MEMMAP_TX_CONTROLBITS_N_BITS 32
C_MEMMAP_TX_CONTROLBITS_BIN_PT 0
C_MEMMAP_TX_DELAYS 0x8024
C_MEMMAP_TX_DELAYS_N_BITS 32
C_MEMMAP_TX_DELAYS_BIN_PT 0
C_MEMMAP_TX_SCALING 0x8028
C_MEMMAP_TX_SCALING_N_BITS 32
C_MEMMAP_TX_SCALING_BIN_PT 0
C_MEMMAP_PKTDET_THRESHOLDS 0x802C
C_MEMMAP_PKTDET_THRESHOLDS_N_BITS 32
C_MEMMAP_PKTDET_THRESHOLDS_BIN_PT 0
C_MEMMAP_PKTDET_DURATIONS 0x8030
C_MEMMAP_PKTDET_DURATIONS_N_BITS 32
C_MEMMAP_PKTDET_DURATIONS_BIN_PT 0
C_MEMMAP_PKTDET_AUTOCORRPARAMS 0x8034
C_MEMMAP_PKTDET_AUTOCORRPARAMS_N_BITS 32
C_MEMMAP_PKTDET_AUTOCORRPARAMS_BIN_PT 0
C_MEMMAP_PKTDET_CONTROLBITS 0x8038
C_MEMMAP_PKTDET_CONTROLBITS_N_BITS 32
C_MEMMAP_PKTDET_CONTROLBITS_BIN_PT 0
C_MEMMAP_RX_AF_TXSCALING 0x803C
C_MEMMAP_RX_AF_TXSCALING_N_BITS 32
C_MEMMAP_RX_AF_TXSCALING_BIN_PT 0
C_MEMMAP_RX_AF_BLANKING 0x8040
C_MEMMAP_RX_AF_BLANKING_N_BITS 32
C_MEMMAP_RX_AF_BLANKING_BIN_PT 0
C_MEMMAP_RX_PILOTCALCPARAMS 0x8044
C_MEMMAP_RX_PILOTCALCPARAMS_N_BITS 32
C_MEMMAP_RX_PILOTCALCPARAMS_BIN_PT 0
C_MEMMAP_RX_CONSTELLATION_SCALING 0x8048
C_MEMMAP_RX_CONSTELLATION_SCALING_N_BITS 32
C_MEMMAP_RX_CONSTELLATION_SCALING_BIN_PT 0
 
Name Value
C_MEMMAP_RX_PKTDET_DELAY 0x804C
C_MEMMAP_RX_PKTDET_DELAY_N_BITS 32
C_MEMMAP_RX_PKTDET_DELAY_BIN_PT 0
C_MEMMAP_RX_CHANEST_MINMAG 0x8050
C_MEMMAP_RX_CHANEST_MINMAG_N_BITS 32
C_MEMMAP_RX_CHANEST_MINMAG_BIN_PT 0
C_MEMMAP_RX_PKTBYTENUMS 0x8054
C_MEMMAP_RX_PKTBYTENUMS_N_BITS 32
C_MEMMAP_RX_PKTBYTENUMS_BIN_PT 0
C_MEMMAP_RX_FIXEDPKTLEN 0x8058
C_MEMMAP_RX_FIXEDPKTLEN_N_BITS 32
C_MEMMAP_RX_FIXEDPKTLEN_BIN_PT 0
C_MEMMAP_RX_PKTDET_LONGCORR_THRESHOLDS 0x805C
C_MEMMAP_RX_PKTDET_LONGCORR_THRESHOLDS_N_BITS 32
C_MEMMAP_RX_PKTDET_LONGCORR_THRESHOLDS_BIN_PT 0
C_MEMMAP_RX_PKTDET_LONGCORR_PARAMS 0x8060
C_MEMMAP_RX_PKTDET_LONGCORR_PARAMS_N_BITS 32
C_MEMMAP_RX_PKTDET_LONGCORR_PARAMS_BIN_PT 0
C_MEMMAP_RX_COARSECFO_CORRECTION 0x8064
C_MEMMAP_RX_COARSECFO_CORRECTION_N_BITS 32
C_MEMMAP_RX_COARSECFO_CORRECTION_BIN_PT 0
C_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION 0x8068
C_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION_N_BITS 32
C_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION_BIN_PT 0
C_MEMMAP_RX_PRECFO_OPTIONS 0x806C
C_MEMMAP_RX_PRECFO_OPTIONS_N_BITS 32
C_MEMMAP_RX_PRECFO_OPTIONS_BIN_PT 0
C_MEMMAP_RX_CONTROLBITS 0x8070
C_MEMMAP_RX_CONTROLBITS_N_BITS 32
C_MEMMAP_RX_CONTROLBITS_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION3 0x8074
C_MEMMAP_TXRX_AUTOREPLY_ACTION3_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION3_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION2 0x8078
C_MEMMAP_TXRX_AUTOREPLY_ACTION2_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION2_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION1 0x807C
C_MEMMAP_TXRX_AUTOREPLY_ACTION1_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION1_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION0 0x8080
C_MEMMAP_TXRX_AUTOREPLY_ACTION0_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION0_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH5 0x8084
C_MEMMAP_TXRX_AUTOREPLY_MATCH5_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH5_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH4 0x8088
C_MEMMAP_TXRX_AUTOREPLY_MATCH4_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH4_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH3 0x808C
C_MEMMAP_TXRX_AUTOREPLY_MATCH3_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH3_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH2 0x8090
C_MEMMAP_TXRX_AUTOREPLY_MATCH2_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH2_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION5 0x8094
C_MEMMAP_TXRX_AUTOREPLY_ACTION5_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION5_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_ACTION4 0x8098
C_MEMMAP_TXRX_AUTOREPLY_ACTION4_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_ACTION4_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH1 0x809C
C_MEMMAP_TXRX_AUTOREPLY_MATCH1_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH1_BIN_PT 0
C_MEMMAP_TXRX_AUTOREPLY_MATCH0 0x80A0
C_MEMMAP_TXRX_AUTOREPLY_MATCH0_N_BITS 32
C_MEMMAP_TXRX_AUTOREPLY_MATCH0_BIN_PT 0
C_MEMMAP_TXMODULATION 0x1000
C_MEMMAP_TXMODULATION_N_BITS 4
C_MEMMAP_TXMODULATION_BIN_PT 0
C_MEMMAP_TXMODULATION_DEPTH 192
C_MEMMAP_TXHEADERTRANSLATE 0x0000
C_MEMMAP_TXHEADERTRANSLATE_N_BITS 10
C_MEMMAP_TXHEADERTRANSLATE_BIN_PT 0
C_MEMMAP_TXHEADERTRANSLATE_DEPTH 1024
C_MEMMAP_CHANNELESTIMATES 0x1400
C_MEMMAP_CHANNELESTIMATES_N_BITS 32
C_MEMMAP_CHANNELESTIMATES_BIN_PT 0
C_MEMMAP_CHANNELESTIMATES_DEPTH 256
C_MEMMAP_RXMODULATION 0x1800
C_MEMMAP_RXMODULATION_N_BITS 4
C_MEMMAP_RXMODULATION_BIN_PT 0
C_MEMMAP_RXMODULATION_DEPTH 192
C_MEMMAP_EVM_PERSYM 0x1C00
C_MEMMAP_EVM_PERSYM_N_BITS 32
C_MEMMAP_EVM_PERSYM_BIN_PT 14
C_MEMMAP_EVM_PERSYM_DEPTH 256
C_MEMMAP_EVM_PERSC 0x2000
C_MEMMAP_EVM_PERSC_N_BITS 32
C_MEMMAP_EVM_PERSC_BIN_PT 22
C_MEMMAP_EVM_PERSC_DEPTH 64
C_MEMMAP_PKTBUFFREQOFFSETS 0x2100
C_MEMMAP_PKTBUFFREQOFFSETS_N_BITS 32
C_MEMMAP_PKTBUFFREQOFFSETS_BIN_PT 32
C_MEMMAP_PKTBUFFREQOFFSETS_DEPTH 32
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Slowest_sync_clk I 1 clk_40_0000MHz
1 Ext_Reset_In I 1 sys_rst_s
2 Dcm_locked I 1 Dcm_all_locked
3 Bus_Struct_Reset O 1 sys_bus_reset
4 Peripheral_Reset O 1 sys_periph_reset
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RESETPPC0 INITIATOR XIL_RESETPPC ppc_reset_bus ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_bridge_slot_2   WARP Radio Board Bridge Core
Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards.

IP Specs
Core Version
radio_bridge 1.30.a


radio_bridge_slot_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 converter_clock_in I 1 clk_40_0000MHz
1 converter_clock_out O 1 fpga_0_radio_bridge_slot_2_converter_clock_out_pin
2 radio_RSSI_ADC_clk O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
3 radio_DAC_I O 1 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
4 radio_DAC_Q O 1 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
5 radio_ADC_I I 1 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
6 radio_ADC_Q I 1 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
7 radio_B O 1 fpga_0_radio_bridge_slot_2_radio_B_pin
8 radio_ANTSW O 1 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
9 radio_LED O 1 fpga_0_radio_bridge_slot_2_radio_LED_pin
10 radio_DIPSW I 1 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
11 radio_RSSI_ADC_D I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
12 radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
13 radio_spi_clk O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
14 radio_spi_data O 1 fpga_0_radio_bridge_slot_2_radio_spi_data_pin
15 radio_spi_cs O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
16 radio_SHDN O 1 fpga_0_radio_bridge_slot_2_radio_SHDN_pin
17 radio_TxEn O 1 fpga_0_radio_bridge_slot_2_radio_TxEn_pin
18 radio_RxEn O 1 fpga_0_radio_bridge_slot_2_radio_RxEn_pin
19 radio_RxHP O 1 fpga_0_radio_bridge_slot_2_radio_RxHP_pin
20 radio_24PA O 1 fpga_0_radio_bridge_slot_2_radio_24PA_pin
21 radio_5PA O 1 fpga_0_radio_bridge_slot_2_radio_5PA_pin
22 radio_RX_ADC_DCS O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
23 radio_RX_ADC_DFS O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
24 radio_RX_ADC_PWDNA O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
25 radio_RX_ADC_PWDNB O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
26 radio_RSSI_ADC_CLAMP O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
27 radio_RSSI_ADC_HIZ O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
28 radio_RSSI_ADC_SLEEP O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
29 radio_LD I 1 fpga_0_radio_bridge_slot_2_radio_LD_pin
30 radio_RX_ADC_OTRA I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
31 radio_RX_ADC_OTRB I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
32 radio_RSSI_ADC_OTR I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
33 radio_DAC_PLL_LOCK I 1 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
34 radio_DAC_RESET O 1 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
35 dac_spi_data O 1 fpga_0_radio_bridge_slot_2_dac_spi_data_pin
36 dac_spi_cs O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
37 dac_spi_clk O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
38 user_ADC_I O 1 radio_bridge_slot_2_user_ADC_I
39 user_ADC_Q O 1 radio_bridge_slot_2_user_ADC_Q
40 user_DAC_I I 1 radio_bridge_slot_2_user_DAC_I
41 user_DAC_Q I 1 radio_bridge_slot_2_user_DAC_Q
42 user_RSSI_ADC_clk I 1 rssi_pkt_detect_plbw_0_rssi_clk_out
43 user_RSSI_ADC_D O 1 radio_bridge_slot_2_user_RSSI_ADC_D
44 user_RxRF_gain I 1 agc_g_rf_a
45 user_RxBB_gain I 1 agc_g_bb_a
46 user_TxModelStart O 1 radio2_txStart
47 user_EEPROM_IO_T I 1 radio_bridge_slot_2_user_EEPROM_IO_T
48 user_EEPROM_IO_O I 1 radio_bridge_slot_2_user_EEPROM_IO_O
49 user_EEPROM_IO_I O 1 radio_bridge_slot_2_user_EEPROM_IO_I
50 user_RxHP_external I 1 agc_rxhp_a
51 user_TxEn_external I 1 ofdm_txen
52 user_RxEn_external I 1 ofdm_rxen
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD TARGET WARP_RC2RB_V1 rc2rb_rad2 radio_controller_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_bridge_slot_3   WARP Radio Board Bridge Core
Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards.

IP Specs
Core Version
radio_bridge 1.30.a


radio_bridge_slot_3 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 converter_clock_in I 1 clk_40_0000MHz
1 converter_clock_out O 1 fpga_0_radio_bridge_slot_3_converter_clock_out_pin
2 radio_RSSI_ADC_clk O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
3 radio_DAC_I O 1 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
4 radio_DAC_Q O 1 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
5 radio_ADC_I I 1 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
6 radio_ADC_Q I 1 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
7 radio_B O 1 fpga_0_radio_bridge_slot_3_radio_B_pin
8 radio_ANTSW O 1 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
9 radio_LED O 1 fpga_0_radio_bridge_slot_3_radio_LED_pin
10 radio_DIPSW I 1 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
11 radio_RSSI_ADC_D I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
12 radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
13 radio_spi_clk O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
14 radio_spi_data O 1 fpga_0_radio_bridge_slot_3_radio_spi_data_pin
15 radio_spi_cs O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
16 radio_SHDN O 1 fpga_0_radio_bridge_slot_3_radio_SHDN_pin
17 radio_TxEn O 1 fpga_0_radio_bridge_slot_3_radio_TxEn_pin
18 radio_RxEn O 1 fpga_0_radio_bridge_slot_3_radio_RxEn_pin
19 radio_RxHP O 1 fpga_0_radio_bridge_slot_3_radio_RxHP_pin
20 radio_24PA O 1 fpga_0_radio_bridge_slot_3_radio_24PA_pin
21 radio_5PA O 1 fpga_0_radio_bridge_slot_3_radio_5PA_pin
22 radio_RX_ADC_DCS O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
23 radio_RX_ADC_DFS O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
24 radio_RX_ADC_PWDNA O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
25 radio_RX_ADC_PWDNB O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
26 radio_RSSI_ADC_CLAMP O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
27 radio_RSSI_ADC_HIZ O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
28 radio_RSSI_ADC_SLEEP O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
29 radio_LD I 1 fpga_0_radio_bridge_slot_3_radio_LD_pin
30 radio_RX_ADC_OTRA I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
31 radio_RX_ADC_OTRB I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
32 radio_RSSI_ADC_OTR I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
33 radio_DAC_PLL_LOCK I 1 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
34 radio_DAC_RESET O 1 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
35 dac_spi_data O 1 fpga_0_radio_bridge_slot_3_dac_spi_data_pin
36 dac_spi_cs O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
37 dac_spi_clk O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
38 user_ADC_I O 1 radio_bridge_slot_3_user_ADC_I
39 user_ADC_Q O 1 radio_bridge_slot_3_user_ADC_Q
40 user_DAC_I I 1 radio_bridge_slot_3_user_DAC_I
41 user_DAC_Q I 1 radio_bridge_slot_3_user_DAC_Q
42 user_RSSI_ADC_clk I 1 rssi_pkt_detect_plbw_0_rssi_clk_out
43 user_RSSI_ADC_D O 1 radio_bridge_slot_3_user_RSSI_ADC_D
44 user_RxRF_gain I 1 agc_g_rf_b
45 user_RxBB_gain I 1 agc_g_bb_b
46 user_EEPROM_IO_T I 1 radio_bridge_slot_3_user_EEPROM_IO_T
47 user_EEPROM_IO_O I 1 radio_bridge_slot_3_user_EEPROM_IO_O
48 user_EEPROM_IO_I O 1 radio_bridge_slot_3_user_EEPROM_IO_I
49 user_RxHP_external I 1 agc_rxhp_b
50 user_TxModelStart O 1 radio3_txStart
51 user_TxEn_external I 1 ofdm_txen
52 user_RxEn_external I 1 ofdm_rxen
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD TARGET WARP_RC2RB_V1 rc2rb_rad3 radio_controller_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_controller_0   WARP Radio Controller (PLB46)


IP Specs
Core Version
radio_controller 1.30.a


radio_controller_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD2 INITIATOR WARP_RC2RB_V1 rc2rb_rad2 radio_bridge_slot_2
RC2RB_RAD3 INITIATOR WARP_RC2RB_V1 rc2rb_rad3 radio_bridge_slot_3
SPLB SLAVE PLBV46 plb_32b_40MHz 4 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xCAC00000
C_HIGHADDR 0xCAC0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_FAMILY virtex4
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


rate_change_filters_plbw_0


IP Specs
Core Version
rate_change_filters_txrx_2ch_plbw 2.00.a


rate_change_filters_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 rxa_i_40m I 1 radio_bridge_slot_2_user_ADC_I
1 rxa_q_40m I 1 radio_bridge_slot_2_user_ADC_Q
2 rxb_i_40m I 1 radio_bridge_slot_3_user_ADC_I
3 rxb_q_40m I 1 radio_bridge_slot_3_user_ADC_Q
4 rxa_i_10m O 1 radio_bridge_slot_2_user_ADC_I_filt
5 rxa_q_10m O 1 radio_bridge_slot_2_user_ADC_Q_filt
6 rxb_i_10m O 1 radio_bridge_slot_3_user_ADC_I_filt
7 rxb_q_10m O 1 radio_bridge_slot_3_user_ADC_Q_filt
8 txa_i_10m I 1 ofdmtx_prefilt_anta_i
9 txa_q_10m I 1 ofdmtx_prefilt_anta_q
10 txb_i_10m I 1 ofdmtx_prefilt_antb_i
11 txb_q_10m I 1 ofdmtx_prefilt_antb_q
12 txa_i_40m O 1 ofdmtx_postfilt_anta_i
13 txa_q_40m O 1 ofdmtx_postfilt_anta_q
14 txb_i_40m O 1 ofdmtx_postfilt_antb_i
15 txb_q_40m O 1 ofdmtx_postfilt_antb_q
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xC5200000
C_HIGHADDR 0xC520FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 1
 
Name Value
C_SPLB_SUPPORT_BURSTS 0
C_MEMMAP_COEFCOUNTER 0x800
C_MEMMAP_COEFCOUNTER_N_BITS 32
C_MEMMAP_COEFCOUNTER_BIN_PT 0
C_MEMMAP_FILTEROPTIONS 0x800
C_MEMMAP_FILTEROPTIONS_N_BITS 32
C_MEMMAP_FILTEROPTIONS_BIN_PT 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


rs232_db9   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.02.a IP


rs232_db9 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_rs232_db9_RX_pin
1 TX O 1 fpga_0_rs232_db9_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84020000
C_HIGHADDR 0x8402FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 57600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


rs232_usb   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.02.a IP


rs232_usb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_rs232_usb_RX_pin
1 TX O 1 fpga_0_rs232_usb_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84000000
C_HIGHADDR 0x8400FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 57600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


warp_timer_plbw_0


IP Specs
Core Version
warp_timer_plbw 2.00.a


warp_timer_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 idlefordifs I 1 ofdm_pktDetector_mimo_plbw_0_idlefordifs
1 timer0_active O 1 debug_timer0_active
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xCD400000
C_HIGHADDR 0xCD40FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_MEMMAP_TIMER_STATUS 0x834
C_MEMMAP_TIMER_STATUS_N_BITS 32
C_MEMMAP_TIMER_STATUS_BIN_PT 0
C_MEMMAP_TIMER0_SLOTCOUNT 0x800
C_MEMMAP_TIMER0_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER0_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER_CONTROL 0x804
C_MEMMAP_TIMER_CONTROL_N_BITS 32
C_MEMMAP_TIMER_CONTROL_BIN_PT 0
C_MEMMAP_TIMER4_SLOTCOUNT 0x808
C_MEMMAP_TIMER4_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER4_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER6_SLOTCOUNT 0x80C
C_MEMMAP_TIMER6_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER6_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER7_SLOTCOUNT 0x810
C_MEMMAP_TIMER7_SLOTCOUNT_N_BITS 32
 
Name Value
C_MEMMAP_TIMER7_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER5_SLOTCOUNT 0x814
C_MEMMAP_TIMER5_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER5_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER2_SLOTCOUNT 0x818
C_MEMMAP_TIMER2_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER2_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMER3_SLOTCOUNT 0x81C
C_MEMMAP_TIMER3_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER3_SLOTCOUNT_BIN_PT 0
C_MEMMAP_TIMERS67_SLOTTIME 0x820
C_MEMMAP_TIMERS67_SLOTTIME_N_BITS 32
C_MEMMAP_TIMERS67_SLOTTIME_BIN_PT 0
C_MEMMAP_TIMERS45_SLOTTIME 0x824
C_MEMMAP_TIMERS45_SLOTTIME_N_BITS 32
C_MEMMAP_TIMERS45_SLOTTIME_BIN_PT 0
C_MEMMAP_TIMERS23_SLOTTIME 0x828
C_MEMMAP_TIMERS23_SLOTTIME_N_BITS 32
C_MEMMAP_TIMERS23_SLOTTIME_BIN_PT 0
C_MEMMAP_TIMERS01_SLOTTIME 0x82C
C_MEMMAP_TIMERS01_SLOTTIME_N_BITS 32
C_MEMMAP_TIMERS01_SLOTTIME_BIN_PT 0
C_MEMMAP_TIMER1_SLOTCOUNT 0x830
C_MEMMAP_TIMER1_SLOTCOUNT_N_BITS 32
C_MEMMAP_TIMER1_SLOTCOUNT_BIN_PT 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_central_dma_0   XPS Central DMA Controller
Simple Direct Memory Access (DMA) services for PLBV46

IP Specs
Core Version Documentation
xps_central_dma 2.03.a IP


xps_central_dma_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MPLB MASTER PLBV46 plb 12 Peripherals.
SPLB SLAVE PLBV46 plb 12 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FIFO_DEPTH 32
C_RD_BURST_SIZE 8
C_WR_BURST_SIZE 8
C_BASEADDR 0x80200000
C_HIGHADDR 0x8020FFFF
C_SPLB_DWIDTH 32
C_SPLB_AWIDTH 32
C_SPLB_NUM_MASTERS 1
 
Name Value
C_SPLB_MID_WIDTH 1
C_SPLB_P2P 0
C_SPLB_NATIVE_DWIDTH 32
C_MPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MPLB_AWIDTH 32
C_MPLB_DWIDTH 32
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOC

analog_bridge_slot_4


IP Specs
Core Version
analog_bridge 1.00.a


analog_bridge_slot_4 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 clock_out O 1 fpga_0_analog_bridge_slot_4_clock_out
1 analog_DAC1_A O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_A
2 analog_DAC1_B O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_B
3 analog_DAC2_A O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_A
4 analog_DAC2_B O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_B
5 analog_DAC1_sleep O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep
6 analog_DAC2_sleep O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep
7 analog_ADC_A I 1 fpga_0_analog_bridge_slot_4_analog_ADC_A
8 analog_ADC_B I 1 fpga_0_analog_bridge_slot_4_analog_ADC_B
9 analog_ADC_DFS O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS
10 analog_ADC_DCS O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS
11 analog_ADC_pdwnA O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA
12 analog_ADC_pdwnB O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB
13 analog_ADC_otrA I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA
14 analog_ADC_otrB I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB
15 analog_LED O 1 fpga_0_analog_bridge_slot_4_analog_LED
16 clock_in I 1 clk_40_0000MHz
17 user_DAC1_A I 1 ofdm_rx_debug_eq_i
18 user_DAC1_B I 1 ofdm_rx_debug_eq_q
19 user_DAC2_A I 1 rx_debug_phasecorrect
20 user_DAC2_B I 1 rx_debug_phaseerr


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


clk_board_config   WARP Clock Board Configuration Core
Configures the Clock Board after FPGA configuration- requied to use the Clock Board oscillators as the master FPGA clock, sampling clock for Radio Boards and RF refence clock for Radio Boards.

IP Specs
Core Version
clock_board_config 1.05.a


clk_board_config IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 sys_clk I 1 fpga_0_clk_board_config_sys_clk_pin
1 sys_rst I 1 net_gnd
2 cfg_radio_dat_out O 1 fpga_0_clk_board_config_cfg_radio_dat_out_pin
3 cfg_radio_csb_out O 1 fpga_0_clk_board_config_cfg_radio_csb_out_pin
4 cfg_radio_en_out O 1 fpga_0_clk_board_config_cfg_radio_en_out_pin
5 cfg_radio_clk_out O 1 fpga_0_clk_board_config_cfg_radio_clk_out_pin
6 cfg_logic_dat_out O 1 fpga_0_clk_board_config_cfg_logic_dat_out_pin
7 cfg_logic_csb_out O 1 fpga_0_clk_board_config_cfg_logic_csb_out_pin
8 cfg_logic_en_out O 1 fpga_0_clk_board_config_cfg_logic_en_out_pin
9 cfg_logic_clk_out O 1 fpga_0_clk_board_config_cfg_logic_clk_out_pin
10 config_invalid O 1 clk_board_config_config_invalid
11 radio_clk_src_sel I 1 radio2_dipsw_zero
12 logic_clk_src_sel I 1 radio2_dipsw_one


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
radio_clk_source_sel_mode 0
logic_clk_source_sel_mode 0
fpga_radio_clk_source 0
fpga_logic_clk_source 0
radio_clk_out4_mode 0x01FF
radio_clk_out5_mode 0x1EFF
radio_clk_out6_mode 0x1EFF
radio_clk_out7_mode 0x01FF
logic_clk_out0_mode 0x02FF
logic_clk_out1_mode 0x02FF
 
Name Value
logic_clk_out2_mode 0x08FF
logic_clk_out3_mode 0x08FF
radio_clk_forward_out_mode 0x0BFF
logic_clk_forward_out_mode 0x1FFF
sys_clk_freq_hz 0x05F5E100
scp_min_freq_hz 0x002625A0
scp_cyc_leng_a 0x00000028
scp_cyc_leng_b 0x00000028
scp_cyc_leng 0x00000028
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKIN I 1 CLK_S
1 CLKOUT0 O 1 clk_125_0000MHz
2 CLKOUT1 O 1 clk_200_0000MHz
3 CLKOUT2 O 1 clk_160_0000MHzDCM0
4 CLKOUT3 O 1 clk_40_0000MHz
5 CLKOUT4 O 1 clk_80_0000MHzDCM0
6 RST I 1 clk_board_config_config_invalid
7 LOCKED O 1 Dcm_all_locked


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 40000000
C_CLKOUT0_FREQ 125000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP NONE
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 200000000
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 160000000
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP DCM0
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 40000000
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 80000000
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP DCM0
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_bus_split_0   Utility Bus Split
Bus splitting primitive

IP Specs
Core Version Documentation
util_bus_split 1.00.a IP


util_bus_split_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Sig I 1 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
1 Out1 O 1 radio2_dipsw_zero & radio2_dipsw_one


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SIZE_IN 4
C_LEFT_POS 0
C_SPLIT 2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_reduced_logic_0   Utility Reduced Logic
Get 1 bit result from 2 input bits

IP Specs
Core Version Documentation
util_reduced_logic 1.00.a IP


util_reduced_logic_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Op1 I 1 radio2_txStart & radio3_txStart
1 Res O 1 txPHYStart


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION or
C_SIZE 2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_reduced_logic_1   Utility Reduced Logic
Get 1 bit result from 2 input bits

IP Specs
Core Version Documentation
util_reduced_logic 1.00.a IP


util_reduced_logic_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Op1 I 1 rx_extpktdet_in1 & rx_extpktdet_in2
1 Res O 1 rx_extpktdet


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION or
C_SIZE 2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_reduced_logic_2   Utility Reduced Logic
Get 1 bit result from 2 input bits

IP Specs
Core Version Documentation
util_reduced_logic 1.00.a IP


util_reduced_logic_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Op1 I 1 debug_pktDetRSSI & debug_pktDetAutoCorr
1 Res O 1 debug_pktDetOut


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_OPERATION or
C_SIZE 2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOC


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.