BlockDiagram

EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk
1GLB debug O 0:8 debug_tx_pktrunning & debug_rx_payload & rssi_pkt_detect_plbw_0_rssi_pkt_det_out & rx_int_goodpkt & rx_int_badpkt & rx_int_goodheader & ofdm_txrx_mimo_plbw_0_rx_int_badheader & rx_pktdetreset & debug_timer0_active
2A fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin I 7:0 fpga_0_TriMode_MAC_GMII_GMII_RXD_0
3A fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
4A fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
5A fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
6A fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
7A fpga_0_TriMode_MAC_GMII_MDIO_0_pin IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0
8A fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin O 7:0 fpga_0_TriMode_MAC_GMII_GMII_TXD_0
9A fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
10A fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
11A fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
12A fpga_0_TriMode_MAC_GMII_MDC_0_pin O 1 fpga_0_TriMode_MAC_GMII_MDC_0
13A fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
14B fpga_0_analog_bridge_slot_4_analog_ADC_A_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_A
15B fpga_0_analog_bridge_slot_4_analog_ADC_B_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_B
16B fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA
17B fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB
18B fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS
19B fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS
20B fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA
21B fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB
22B fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_A
23B fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_B
24B fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep
25B fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_A
26B fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_B
27B fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep
28B fpga_0_analog_bridge_slot_4_analog_LED_pin O 0:2 fpga_0_analog_bridge_slot_4_analog_LED
29B fpga_0_analog_bridge_slot_4_clock_out_pin O 1 fpga_0_analog_bridge_slot_4_clock_out
30C fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out
31C fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out
32C fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out
33C fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out
34C fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out
35C fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out
36C fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out
37C fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out
38D sys_clk_pin I 1 dcm_clk_s  CLK 
39E debug_GPIO_d_out_pin O 0:3 fpga_0_debug_GPIO_d_out
40F fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0
41G debug_chipscopetrig_pin I 1 debug_chipscopetrig
42G debug_extTxStart_pin I 1 debug_extTxStart
43H sys_rst_pin I 1 sys_rst_s  RESET 
44I fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_I
45I fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_Q
46I fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_2_radio_DIPSW
47I fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD
48I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D
49I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR
50I fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA
51I fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB
52I fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK
53I fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO
54I fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out
55I fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk
56I fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs
57I fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data
58I fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA
59I fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA
60I fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_2_radio_ANTSW
61I fpga_0_radio_bridge_slot_2_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_2_radio_B
62I fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_I
63I fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_Q
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
64I fpga_0_radio_bridge_slot_2_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_2_radio_LED
65I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP
66I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ
67I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP
68I fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk
69I fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS
70I fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS
71I fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA
72I fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB
73I fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn
74I fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP
75I fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN
76I fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn
77I fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET
78I fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk
79I fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs
80I fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data
81J fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_I
82J fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_Q
83J fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_3_radio_DIPSW
84J fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD
85J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D
86J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR
87J fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA
88J fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB
89J fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK
90J fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO
91J fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out
92J fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk
93J fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs
94J fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data
95J fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA
96J fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA
97J fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_3_radio_ANTSW
98J fpga_0_radio_bridge_slot_3_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_3_radio_B
99J fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_I
100J fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_Q
101J fpga_0_radio_bridge_slot_3_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_3_radio_LED
102J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP
103J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ
104J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP
105J fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk
106J fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS
107J fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS
108J fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA
109J fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB
110J fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn
111J fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP
112J fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN
113J fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn
114J fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET
115J fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk
116J fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs
117J fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data
118K fpga_0_rs232_db9_RX_pin I 1 fpga_0_rs232_db9_RX
119K fpga_0_rs232_db9_TX_pin O 1 fpga_0_rs232_db9_TX
120L fpga_0_rs232_usb_RX_pin I 1 fpga_0_rs232_usb_RX
121L fpga_0_rs232_usb_TX_pin O 1 fpga_0_rs232_usb_TX
122M fpga_0_warp_v4_userio_all_DIPSW_in_pin I 0:3 fpga_0_warp_v4_userio_all_DIPSW_in
123M fpga_0_warp_v4_userio_all_PB_in_pin I 0:3 fpga_0_warp_v4_userio_all_PB_in
124M fpga_0_warp_v4_userio_all_IOEx_SCL_pin O 1 fpga_0_warp_v4_userio_all_IOEx_SCL
125M fpga_0_warp_v4_userio_all_IOEx_SDA_pin O 1 fpga_0_warp_v4_userio_all_IOEx_SDA
126M fpga_0_warp_v4_userio_all_LEDs_out_pin O 0:7 fpga_0_warp_v4_userio_all_LEDs_out