BlockDiagram

EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB fpga_0_USER_IO_GPIO_in_pin I 0:7 fpga_0_USER_IO_GPIO_in
1GLB debug O 0:8 debug_tx_pktrunning & debug_rx_payload & rssi_pkt_detect_plbw_0_rssi_pkt_det_out & rx_int_goodpkt & rx_int_badpkt & rx_int_goodheader & ofdm_txrx_mimo_plbw_0_rx_int_badheader & rx_pktdetreset & ofdm_pktDetector_mimo_plbw_0_idlefordifs
2GLB fpga_0_Ethernet_MAC_slew1_pin O 1 net_vcc
3GLB fpga_0_Ethernet_MAC_slew2_pin O 1 net_vcc
4GLB fpga_0_SRAM0_CLOCK O 1 sys_clk_s
5GLB fpga_0_SRAM1_CLOCK O 1 sys_clk_s
6A fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col
7A fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs
8A fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv
9A fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk
10A fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data
11A fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er
12A fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk
13A fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n
14A fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data
15A fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en
16B fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ
17B fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN
18B fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN
19B fpga_0_SRAM0_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CE
20B fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN
21B fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN
22B fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN
23C fpga_0_SRAM0_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM0_ZBT_512Kx32_Mem_A
24D fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ
25D fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN
26D fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN
27D fpga_0_SRAM1_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CE
28D fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN
29D fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN
30D fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN
31E fpga_0_SRAM1_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM1_ZBT_512Kx32_Mem_A
32F fpga_0_USER_IO_GPIO2_d_out_pin O 0:17 fpga_0_USER_IO_GPIO2_d_out
33G fpga_0_analog_bridge_slot_4_analog_ADC_A_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_A
34G fpga_0_analog_bridge_slot_4_analog_ADC_B_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_B
35G fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA
36G fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB
37G fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS
38G fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS
39G fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA
40G fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB
41G fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_A
42G fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_B
43G fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep
44G fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_A
45G fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_B
46G fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep
47G fpga_0_analog_bridge_slot_4_analog_LED_pin O 0:2 fpga_0_analog_bridge_slot_4_analog_LED
48G fpga_0_analog_bridge_slot_4_clock_out_pin O 1 fpga_0_analog_bridge_slot_4_clock_out
49H fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk
50H fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out
51H fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out
52H fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out
53H fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out
54H fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out
55H fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out
56H fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out
57H fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out
58I sys_clk_pin I 1 dcm_clk_s  CLK 
59J debug_GPIO_d_out_pin O 0:3 fpga_0_debug_GPIO_d_out
60K fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0
61L debug_chipscopetrig_pin I 1 debug_chipscopetrig
62M sys_rst_pin I 1 sys_rst_s  RESET 
63N fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_I
64N fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_Q
65N fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_2_radio_DIPSW
66N fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD
67N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D
68N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR
69N fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA
70N fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB
71N fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK
72N fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO
73N fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out
74N fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk
75N fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs
76N fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data
77N fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA
78N fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA
79N fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_2_radio_ANTSW
80N fpga_0_radio_bridge_slot_2_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_2_radio_B
81N fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_I
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
82N fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_Q
83N fpga_0_radio_bridge_slot_2_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_2_radio_LED
84N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP
85N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ
86N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP
87N fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk
88N fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS
89N fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS
90N fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA
91N fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB
92N fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn
93N fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP
94N fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN
95N fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn
96N fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET
97N fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk
98N fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs
99N fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data
100O fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_I
101O fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_Q
102O fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_3_radio_DIPSW
103O fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD
104O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D
105O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR
106O fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA
107O fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB
108O fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK
109O fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO
110O fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out
111O fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk
112O fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs
113O fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data
114O fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA
115O fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA
116O fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_3_radio_ANTSW
117O fpga_0_radio_bridge_slot_3_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_3_radio_B
118O fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_I
119O fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_Q
120O fpga_0_radio_bridge_slot_3_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_3_radio_LED
121O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP
122O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ
123O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP
124O fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk
125O fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS
126O fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS
127O fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA
128O fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB
129O fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn
130O fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP
131O fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN
132O fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn
133O fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET
134O fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk
135O fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs
136O fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data
137P fpga_0_rs232_RX_pin I 1 fpga_0_rs232_RX
138P fpga_0_rs232_TX_pin O 1 fpga_0_rs232_TX
139Q fpga_0_sysace_compactflash_SysACE_CLK_pin I 1 fpga_0_sysace_compactflash_SysACE_CLK
140Q fpga_0_sysace_compactflash_SysACE_MPIRQ_pin I 1 fpga_0_sysace_compactflash_SysACE_MPIRQ
141Q fpga_0_sysace_compactflash_SysACE_MPD_pin IO 15:0 fpga_0_sysace_compactflash_SysACE_MPD
142Q fpga_0_sysace_compactflash_SysACE_CEN_pin O 1 fpga_0_sysace_compactflash_SysACE_CEN
143Q fpga_0_sysace_compactflash_SysACE_MPA_pin O 6:0 fpga_0_sysace_compactflash_SysACE_MPA
144Q fpga_0_sysace_compactflash_SysACE_OEN_pin O 1 fpga_0_sysace_compactflash_SysACE_OEN
145Q fpga_0_sysace_compactflash_SysACE_WEN_pin O 1 fpga_0_sysace_compactflash_SysACE_WEN
146R user_io_board_controller_plbw_0_buttons_big_pin I 0:1 user_io_board_controller_plbw_0_buttons_big
147R user_io_board_controller_plbw_0_buttons_small_pin I 0:5 user_io_board_controller_plbw_0_buttons_small
148R user_io_board_controller_plbw_0_dip_switch_pin I 0:3 user_io_board_controller_plbw_0_dip_switch
149R user_io_board_controller_plbw_0_trackball_ox_pin I 1 user_io_board_controller_plbw_0_trackball_ox
150R user_io_board_controller_plbw_0_trackball_oxn_pin I 1 user_io_board_controller_plbw_0_trackball_oxn
151R user_io_board_controller_plbw_0_trackball_oy_pin I 1 user_io_board_controller_plbw_0_trackball_oy
152R user_io_board_controller_plbw_0_trackball_oyn_pin I 1 user_io_board_controller_plbw_0_trackball_oyn
153R user_io_board_controller_plbw_0_trackball_sel2_pin I 1 user_io_board_controller_plbw_0_trackball_sel2
154R user_io_board_controller_plbw_0_buzzer_pin O 1 user_io_board_controller_plbw_0_buzzer
155R user_io_board_controller_plbw_0_cs_pin O 1 user_io_board_controller_plbw_0_cs
156R user_io_board_controller_plbw_0_leds_pin O 0:7 user_io_board_controller_plbw_0_leds
157R user_io_board_controller_plbw_0_resetlcd_pin O 1 user_io_board_controller_plbw_0_resetlcd
158R user_io_board_controller_plbw_0_scl_pin O 1 user_io_board_controller_plbw_0_scl
159R user_io_board_controller_plbw_0_sdi_pin O 1 user_io_board_controller_plbw_0_sdi
160R user_io_board_controller_plbw_0_trackball_sel1_pin O 1 user_io_board_controller_plbw_0_trackball_sel1
161R user_io_board_controller_plbw_0_trackball_xscn_pin O 1 user_io_board_controller_plbw_0_trackball_xscn
162R user_io_board_controller_plbw_0_trackball_yscn_pin O 1 user_io_board_controller_plbw_0_trackball_yscn