EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_2_radio_ANTSW fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_2_radio_DIPSW fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD fpga_0_radio_bridge_slot_2_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_2_radio_LED fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data fpga_0_radio_bridge_slot_2_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_2_radio_B fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_I fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_Q fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_I fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_Q fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_3_radio_ANTSW fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_3_radio_DIPSW fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD fpga_0_radio_bridge_slot_3_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_3_radio_LED fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data fpga_0_radio_bridge_slot_3_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_3_radio_B fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_I fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_Q fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_I fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_Q fpga_0_USER_IO_GPIO2_d_out_pin O 0:17 fpga_0_USER_IO_GPIO2_d_out fpga_0_USER_IO_GPIO_in_pin I 0:7 fpga_0_USER_IO_GPIO_in fpga_0_rs232_RX_pin I 1 fpga_0_rs232_RX fpga_0_rs232_TX_pin O 1 fpga_0_rs232_TX fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0 fpga_0_Ethernet_MAC_slew1_pin O 1 net_vcc fpga_0_Ethernet_MAC_slew2_pin O 1 net_vcc fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data fpga_0_user_io_board_controller_slot1_sdi_pin O 1 fpga_0_user_io_board_controller_slot1_sdi fpga_0_user_io_board_controller_slot1_scl_pin O 1 fpga_0_user_io_board_controller_slot1_scl fpga_0_user_io_board_controller_slot1_resetlcd_pin O 1 fpga_0_user_io_board_controller_slot1_resetlcd fpga_0_user_io_board_controller_slot1_cs_pin O 1 fpga_0_user_io_board_controller_slot1_cs fpga_0_user_io_board_controller_slot1_buzzer_pin O 1 fpga_0_user_io_board_controller_slot1_buzzer fpga_0_user_io_board_controller_slot1_trackball_yscn_pin O 1 fpga_0_user_io_board_controller_slot1_trackball_yscn fpga_0_user_io_board_controller_slot1_trackball_sel1_pin O 1 fpga_0_user_io_board_controller_slot1_trackball_sel1 fpga_0_user_io_board_controller_slot1_trackball_xscn_pin O 1 fpga_0_user_io_board_controller_slot1_trackball_xscn fpga_0_user_io_board_controller_slot1_trackball_sel2_pin I 1 fpga_0_user_io_board_controller_slot1_trackball_sel2 fpga_0_user_io_board_controller_slot1_trackball_oyn_pin I 1 fpga_0_user_io_board_controller_slot1_trackball_oyn fpga_0_user_io_board_controller_slot1_trackball_oy_pin I 1 fpga_0_user_io_board_controller_slot1_trackball_oy fpga_0_user_io_board_controller_slot1_trackball_oxn_pin I 1 fpga_0_user_io_board_controller_slot1_trackball_oxn fpga_0_user_io_board_controller_slot1_trackball_ox_pin I 1 fpga_0_user_io_board_controller_slot1_trackball_ox fpga_0_user_io_board_controller_slot1_leds_pin O 0:7 fpga_0_user_io_board_controller_slot1_leds fpga_0_user_io_board_controller_slot1_dip_switch_pin I 0:3 fpga_0_user_io_board_controller_slot1_dip_switch fpga_0_user_io_board_controller_slot1_buttons_small_pin I 0:5 fpga_0_user_io_board_controller_slot1_buttons_small fpga_0_user_io_board_controller_slot1_buttons_big_pin I 0:1 fpga_0_user_io_board_controller_slot1_buttons_big sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET  debug O 0:2 rxrun & txrun & agcsetdone