Overview
Block Diagram
External Ports
 Processor
   ppc405_0
 Busses
   plb
   plb_v46_40MHz
   ppc405_0_docm
   ppc405_0_iocm
 Bridge
   plbv46_plbv46_bridge_0
 Memorys
   plb_bram_if_cntlr_1_bram
   ppc405_0_docm_cntlr_bram
   ppc405_0_iocm_cntlr_bram
 Memory Controllers
   ppc405_0_docm_cntlr
   ppc405_0_iocm_cntlr
   xps_bram_if_cntlr_1
 Peripherals
   TriMode_MAC_GMII
   TriMode_MAC_GMII_fifo
   UserIO
   eeprom_controller
   jtagppc_cntlr_inst
   proc_sys_reset_0
   radio_bridge_slot_2
   radio_bridge_slot_3
   radio_controller_0
   rs232_db9
   rs232_usb
   warplab_mimo_4x4_agc_plbw_0
   warplab_mimo_4x4_plbw_0
   xps_central_dma_0
   xps_timer_0
 IP
   clk_board_config
   clock_generator_0
Timing Information