Printable Version
Overview
Resources Used
1   PowerPC 405 Virtex-4
1   Instruction-Side On-Chip Memory (OCM) Bus 1.0
1   Data-Side On-Chip Memory (OCM) Bus 1.0
2   Processor Local Bus (PLB) 4.6
1   PLBV46 to PLBV46 Bridge
3   Block RAM (BRAM) Block
1   Instruction-Side OCM BRAM Controller
1   Data-Side OCM BRAM Controller
1   XPS BRAM Controller
2   XPS UART (Lite)
1   XPS LocalLink Tri-mode Ethernet MAC
1   WARP Clock Board Configuration Core
1   WARP Radio Controller (PLB46)
2   WARP Radio Board Bridge Core
1   EEPROM Controller based on Maxim OneWire Master core
1   XPS LocalLink FIFO
1   Clock Generator
1   PowerPC JTAG Controller
1   Processor System Reset Module
1   XPS Central DMA Controller
1   XPS Timer/Counter
Specifics
Generated Thu Jul 12 14:34:05 2012
EDK Version 13.4
Device Family virtex4
Device xc4vfx100ff1517-11

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
SHARED fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
SHARED fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
SHARED fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin I 0:7 fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MDIO_0_pin IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin O 0:7 fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_MDC_0_pin O 1 fpga_0_TriMode_MAC_GMII_MDC_0_pin
TriMode_MAC_GMII fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
UserIO fpga_0_UserIO_DIPSW_in_pin I 3:0 fpga_0_UserIO_DIPSW_in_pin
UserIO fpga_0_UserIO_PB_in_pin I 3:0 fpga_0_UserIO_PB_in_pin
UserIO fpga_0_UserIO_IOEx_SCL_pin O 1 fpga_0_UserIO_IOEx_SCL_pin
UserIO fpga_0_UserIO_IOEx_SDA_pin O 1 fpga_0_UserIO_IOEx_SDA_pin
UserIO fpga_0_UserIO_LEDs_out_pin O 7:0 fpga_0_UserIO_LEDs_out_pin
clk_board_config fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out_pin
clk_board_config fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out_pin
clk_board_config fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 CLK_S  CLK 
eeprom_controller fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0_pin
proc_sys_reset_0 fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_2_radio_B_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_2_radio_LED_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
radio_bridge_slot_2 fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_3_radio_B_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_3_radio_LED_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
radio_bridge_slot_3 fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data_pin
rs232_db9 fpga_0_rs232_db9_RX_pin I 1 fpga_0_rs232_db9_RX_pin
rs232_db9 fpga_0_rs232_db9_TX_pin O 1 fpga_0_rs232_db9_TX_pin
rs232_usb fpga_0_rs232_usb_RX_pin I 1 fpga_0_rs232_usb_RX_pin
rs232_usb fpga_0_rs232_usb_TX_pin O 1 fpga_0_rs232_usb_TX_pin


Processors TOP

ppc405_0   PowerPC 405 Virtex-4
A wrapper to instantiate the PowerPC 405 Processor Block primitive

IP Specs
Core Version Documentation
ppc405_virtex4 2.01.b IP


ppc405_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CPMC405CLOCK I 1 clk_160_0000MHzDCM0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DPLB0 MASTER PLBV46 plb 11 Peripherals.
IPLB0 MASTER PLBV46 plb 11 Peripherals.
DSOCM MASTER DSOCM ppc405_0_docm ppc405_0_docm_cntlr
ISOCM MASTER ISOCM ppc405_0_iocm ppc405_0_iocm_cntlr
JTAGPPC TARGET XIL_JTAGPPC ppc405_0_jtagppc_bus jtagppc_cntlr_inst
RESETPPC TARGET XIL_RESETPPC ppc_reset_bus proc_sys_reset_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DPLB0_DWIDTH 64
C_DPLB0_NATIVE_DWIDTH 64
C_IPLB0_DWIDTH 64
C_IPLB0_NATIVE_DWIDTH 64
C_DPLB1_DWIDTH 64
C_DPLB1_NATIVE_DWIDTH 64
C_IPLB1_DWIDTH 64
C_IPLB1_NATIVE_DWIDTH 64
C_DPLB1_ADDR_BASE 0xFFFFFFFF
C_DPLB1_ADDR_HIGH 0x00000000
C_IPLB1_ADDR_BASE 0xFFFFFFFF
C_IPLB1_ADDR_HIGH 0x00000000
C_FASTEST_PLB_CLOCK DPLB0
C_GENERATE_PLB_TIMESPECS 1
C_DPLB0_P2P 1
C_DPLB1_P2P 1
C_IPLB0_P2P 1
C_IPLB1_P2P 1
 
Name Value
C_IDCR_BASEADDR 0B0100000000
C_IDCR_HIGHADDR 0B0111111111
C_DISABLE_OPERAND_FORWARDING 1
C_MMU_ENABLE 1
C_DETERMINISTIC_MULT 0
C_PLBSYNCBYPASS 1
C_APU_CONTROL 0B1101111000000000
C_APU_UDI_1 0B101000011000100110000011
C_APU_UDI_2 0B101000111000100110000011
C_APU_UDI_3 0B101001011000100111000011
C_APU_UDI_4 0B101001111000100111000011
C_APU_UDI_5 0B101010011000110000000011
C_APU_UDI_6 0B101010111000110000000011
C_APU_UDI_7 0B101011011000110001000011
C_APU_UDI_8 0B101011111000110001000011
C_PVR_HIGH 0B0000
C_PVR_LOW 0B0000
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOP

plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.05.a IP


plb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
ppc405_0 MASTER DPLB0
ppc405_0 MASTER IPLB0
xps_central_dma_0 MASTER MPLB
xps_bram_if_cntlr_1 SLAVE SPLB
UserIO SLAVE SPLB
rs232_db9 SLAVE SPLB
rs232_usb SLAVE SPLB
TriMode_MAC_GMII SLAVE SPLB
eeprom_controller SLAVE SPLB
TriMode_MAC_GMII_fifo SLAVE SPLB
plbv46_plbv46_bridge_0 SLAVE SPLB
warplab_mimo_4x4_plbw_0 SLAVE SPLB
xps_central_dma_0 SLAVE SPLB
xps_timer_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0B1111111111
C_HIGHADDR 0B0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 100
C_ADDR_PIPELINING_TYPE 1
C_FAMILY virtex5
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


plb_v46_40MHz   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.05.a IP


plb_v46_40MHz IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_40_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
plbv46_plbv46_bridge_0 MASTER MPLB
radio_controller_0 SLAVE SPLB
warplab_mimo_4x4_agc_plbw_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0B1111111111
C_HIGHADDR 0B0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 100
C_ADDR_PIPELINING_TYPE 1
C_FAMILY virtex5
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_docm   Data-Side On-Chip Memory (OCM) Bus 1.0
Data-Side On-Chip Memory(OCM) bus interconnect core

IP Specs
Core Version Documentation
dsocm_v10 2.00.b IP


ppc405_0_docm IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 DSOCM_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
ppc405_0 MASTER DSOCM
ppc405_0_docm_cntlr SLAVE DSOCM


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_MASTERS 1
C_NUM_SLAVES 1
C_DSCNTLVALUE 0xA3
C_DSARCVALUE 0x31
C_FIXED_LATENCY 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm   Instruction-Side On-Chip Memory (OCM) Bus 1.0
Instruction-side On-Chip Memory(OCM) bus interconnect core

IP Specs
Core Version Documentation
isocm_v10 2.00.b IP


ppc405_0_iocm IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 ISOCM_Clk I 1 clk_80_0000MHzDCM0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
ppc405_0 MASTER ISOCM
ppc405_0_iocm_cntlr SLAVE ISOCM


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_MASTERS 1
C_NUM_SLAVES 1
C_ISCNTLVALUE 0xA3
C_ISARCVALUE 0x30
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Bridges TOP

plbv46_plbv46_bridge_0   PLBV46 to PLBV46 Bridge
PLBV46 to PLBV46 bridge.

IP Specs
Core Version Documentation
plbv46_plbv46_bridge 1.04.a IP


plbv46_plbv46_bridge_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MPLB MASTER PLBV46 plb_v46_40MHz 2 Peripherals.
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_ADDR_RNG 2
C_BRIDGE_BASEADDR 0x86200000
C_BRIDGE_HIGHADDR 0x8620FFFF
C_RNG0_BASEADDR 0xC4A00000
C_RNG0_HIGHADDR 0xC4A0FFFF
C_RNG1_BASEADDR 0xCAC00000
C_RNG1_HIGHADDR 0xCAC0FFFF
C_RNG2_BASEADDR 0xFFFFFFFF
C_RNG2_HIGHADDR 0x00000000
C_RNG3_BASEADDR 0xFFFFFFFF
C_RNG3_HIGHADDR 0x00000000
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SMALLEST_MASTER 32
C_SPLB_BIGGEST_MASTER 32
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_MPLB_AWIDTH 32
C_MPLB_DWIDTH 32
C_SPLB_NATIVE_DWIDTH 32
C_MPLB_NATIVE_DWIDTH 32
C_MPLB_SMALLEST_SLAVE 32
C_BUS_CLOCK_RATIO 2
C_PREFETCH_TIMEOUT 10
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOP

plb_bram_if_cntlr_1_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


plb_bram_if_cntlr_1_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM xps_bram_if_cntlr_1_port xps_bram_if_cntlr_1


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_docm_cntlr_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


ppc405_0_docm_cntlr_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ppc405_0_docm_cntlr_porta ppc405_0_docm_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm_cntlr_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


ppc405_0_iocm_cntlr_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ppc405_0_iocm_cntlr_porta ppc405_0_iocm_cntlr
PORTB TARGET XIL_BRAM ppc405_0_iocm_cntlr_portb ppc405_0_iocm_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOP

ppc405_0_docm_cntlr   Data-Side OCM BRAM Controller
BRAM_Block connects to the DSOCM V10 Bus for Virtex-II Pro PowerPC 405 based embedded systems.

IP Specs
Core Version Documentation
dsbram_if_cntlr 3.00.c IP


ppc405_0_docm_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA INITIATOR XIL_BRAM ppc405_0_docm_cntlr_porta ppc405_0_docm_cntlr_bram
DSOCM SLAVE DSOCM ppc405_0_docm ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x40110000
C_HIGHADDR 0x4011FFFF
C_BRAM_EN 0
C_RANGECHECK 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ppc405_0_iocm_cntlr   Instruction-Side OCM BRAM Controller
BRAM_Block connects to the ISOCM V10 Bus for Virtex-II Pro PowerPC 405 based embedded systems.

IP Specs
Core Version Documentation
isbram_if_cntlr 3.00.c IP


ppc405_0_iocm_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DCR_WRITE_PORT INITIATOR XIL_BRAM ppc405_0_iocm_cntlr_porta ppc405_0_iocm_cntlr_bram
INSTRN_READ_PORT INITIATOR XIL_BRAM ppc405_0_iocm_cntlr_portb ppc405_0_iocm_cntlr_bram
ISOCM SLAVE ISOCM ppc405_0_iocm ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xFFFF0000
C_HIGHADDR 0xFFFFFFFF
C_BRAM_EN 0
C_RANGECHECK 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_bram_if_cntlr_1   XPS BRAM Controller
Attaches BRAM to the PLBV46

IP Specs
Core Version Documentation
xps_bram_if_cntlr 1.00.b IP


xps_bram_if_cntlr_1 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA INITIATOR XIL_BRAM xps_bram_if_cntlr_1_port plb_bram_if_cntlr_1_bram
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000FFFF
C_SPLB_NATIVE_DWIDTH 64
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_NUM_MASTERS 2
 
Name Value
C_SPLB_MID_WIDTH 1
C_SPLB_SUPPORT_BURSTS 1
C_SPLB_P2P 0
C_SPLB_SMALLEST_MASTER 32
C_FAMILY virtex5
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOP

TriMode_MAC_GMII   XPS LocalLink Tri-mode Ethernet MAC


IP Specs
Core Version Documentation
xps_ll_temac 2.03.a IP


TriMode_MAC_GMII IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 TemacPhy_RST_n O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
1 GTX_CLK_0 I 1 clk_125_0000MHz
2 REFCLK I 1 clk_200_0000MHz
3 LlinkTemac0_CLK I 1 clk_80_0000MHzDCM0
4 MII_TX_CLK_0 I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
5 GMII_TXD_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
6 GMII_TX_EN_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
7 GMII_TX_ER_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
8 GMII_TX_CLK_0 O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
9 GMII_RXD_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
10 GMII_RX_DV_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
11 GMII_RX_ER_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
12 GMII_RX_CLK_0 I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
13 MDC_0 O 1 fpga_0_TriMode_MAC_GMII_MDC_0_pin
14 MDIO_0 IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
LLINK0 INITIATOR XIL_LL_DMA TriMode_MAC_GMII_llink0 TriMode_MAC_GMII_fifo
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_IDELAYCTRL 2
C_IDELAYCTRL_LOC IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
C_SUBFAMILY FX
C_RESERVED 0
C_SPLB_NATIVE_DWIDTH 32
C_FAMILY virtex5
C_BASEADDR 0x87000000
C_HIGHADDR 0x8707FFFF
C_SPLB_DWIDTH 32
C_SPLB_AWIDTH 32
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
C_SPLB_P2P 0
C_INCLUDE_IO 1
C_PHY_TYPE 1
C_TEMAC1_ENABLED 0
C_TEMAC0_TXFIFO 4096
C_TEMAC0_RXFIFO 4096
C_TEMAC1_TXFIFO 4096
C_TEMAC1_RXFIFO 4096
C_BUS2CORE_CLK_RATIO 1
C_TEMAC_TYPE 1
C_TEMAC0_TXCSUM 0
C_TEMAC0_RXCSUM 0
 
Name Value
C_TEMAC1_TXCSUM 0
C_TEMAC1_RXCSUM 0
C_TEMAC0_PHYADDR 0B00001
C_TEMAC1_PHYADDR 0B00010
C_TEMAC0_TXVLAN_TRAN 0
C_TEMAC0_RXVLAN_TRAN 0
C_TEMAC1_TXVLAN_TRAN 0
C_TEMAC1_RXVLAN_TRAN 0
C_TEMAC0_TXVLAN_TAG 0
C_TEMAC0_RXVLAN_TAG 0
C_TEMAC1_TXVLAN_TAG 0
C_TEMAC1_RXVLAN_TAG 0
C_TEMAC0_TXVLAN_STRP 0
C_TEMAC0_RXVLAN_STRP 0
C_TEMAC1_TXVLAN_STRP 0
C_TEMAC1_RXVLAN_STRP 0
C_TEMAC0_MCAST_EXTEND 0
C_TEMAC1_MCAST_EXTEND 0
C_TEMAC0_STATS 0
C_TEMAC1_STATS 0
C_TEMAC0_AVB 0
C_TEMAC1_AVB 0
C_SIMULATION 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


TriMode_MAC_GMII_fifo   XPS LocalLink FIFO


IP Specs
Core Version Documentation
xps_ll_fifo 1.02.a IP


TriMode_MAC_GMII_fifo IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.
LLINK TARGET XIL_LL_DMA TriMode_MAC_GMII_llink0 TriMode_MAC_GMII


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SPLB_MID_WIDTH 3
C_SPLB_NUM_MASTERS 8
C_SPLB_SMALLEST_MASTER 128
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_AWIDTH 32
C_BASEADDR 0x81A00000
C_HIGHADDR 0x81A0FFFF
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


UserIO


IP Specs
Core Version
warp_v4_userio 1.00.a


UserIO IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 LEDs_out O 1 fpga_0_UserIO_LEDs_out_pin
1 IOEx_SDA O 1 fpga_0_UserIO_IOEx_SDA_pin
2 IOEx_SCL O 1 fpga_0_UserIO_IOEx_SCL_pin
3 PB_in I 1 fpga_0_UserIO_PB_in_pin
4 DIPSW_in I 1 fpga_0_UserIO_DIPSW_in_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_ADDRESS_0 0x40
C_ADDRESS_1 0x42
C_I2C_DIVIDER 0x40
C_BASEADDR 0xC9600000
C_HIGHADDR 0xC960FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
 
Name Value
C_SPLB_MID_WIDTH 3
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_INCLUDE_DPHASE_TIMER 0
C_FAMILY virtex4
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


eeprom_controller   EEPROM Controller based on Maxim OneWire Master core


IP Specs
Core Version
eeprom_onewire 1.10.a


eeprom_controller IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 DQ0 IO 1 fpga_0_eeprom_controller_DQ0_pin
1 DQ2_T O 1 eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
2 DQ2_O O 1 eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
3 DQ2_I I 1 eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
4 DQ3_T O 1 eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
5 DQ3_O O 1 eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
6 DQ3_I I 1 eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
7 DQ5_I I 1 net_vcc
8 DQ6_I I 1 net_vcc
9 DQ7_I I 1 net_vcc
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
 
Name Value
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_INCLUDE_DPHASE_TIMER 0
C_FAMILY virtex5
C_MEM0_BASEADDR 0xC5400000
C_MEM0_HIGHADDR 0xC540FFFF
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


jtagppc_cntlr_inst   PowerPC JTAG Controller
JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA.

IP Specs
Core Version Documentation
jtagppc_cntlr 2.01.c IP


jtagppc_cntlr_inst IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
JTAGPPC0 INITIATOR XIL_JTAGPPC ppc405_0_jtagppc_bus ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DEVICE X2VP4
C_NUM_PPC_USED 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Slowest_sync_clk I 1 clk_40_0000MHz
1 Ext_Reset_In I 1 sys_rst_s
2 Dcm_locked I 1 Dcm_all_locked
3 Bus_Struct_Reset O 1 sys_bus_reset
4 Peripheral_Reset O 1 sys_periph_reset
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RESETPPC0 INITIATOR XIL_RESETPPC ppc_reset_bus ppc405_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_bridge_slot_2   WARP Radio Board Bridge Core
Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards.

IP Specs
Core Version
radio_bridge 1.30.a


radio_bridge_slot_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 converter_clock_in I 1 clk_40_0000MHz
1 converter_clock_out O 1 fpga_0_radio_bridge_slot_2_converter_clock_out_pin
2 radio_RSSI_ADC_clk O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
3 radio_DAC_I O 1 fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
4 radio_DAC_Q O 1 fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
5 radio_ADC_I I 1 fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
6 radio_ADC_Q I 1 fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
7 radio_B O 1 fpga_0_radio_bridge_slot_2_radio_B_pin
8 radio_ANTSW O 1 fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
9 radio_LED O 1 fpga_0_radio_bridge_slot_2_radio_LED_pin
10 radio_DIPSW I 1 fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
11 radio_RSSI_ADC_D I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
12 radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
13 radio_spi_clk O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
14 radio_spi_data O 1 fpga_0_radio_bridge_slot_2_radio_spi_data_pin
15 radio_spi_cs O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
16 radio_SHDN O 1 fpga_0_radio_bridge_slot_2_radio_SHDN_pin
17 radio_TxEn O 1 fpga_0_radio_bridge_slot_2_radio_TxEn_pin
18 radio_RxEn O 1 fpga_0_radio_bridge_slot_2_radio_RxEn_pin
19 radio_RxHP O 1 fpga_0_radio_bridge_slot_2_radio_RxHP_pin
20 radio_24PA O 1 fpga_0_radio_bridge_slot_2_radio_24PA_pin
21 radio_5PA O 1 fpga_0_radio_bridge_slot_2_radio_5PA_pin
22 radio_RX_ADC_DCS O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
23 radio_RX_ADC_DFS O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
24 radio_RX_ADC_PWDNA O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
25 radio_RX_ADC_PWDNB O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
26 radio_RSSI_ADC_CLAMP O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
27 radio_RSSI_ADC_HIZ O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
28 radio_RSSI_ADC_SLEEP O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
29 radio_LD I 1 fpga_0_radio_bridge_slot_2_radio_LD_pin
30 radio_RX_ADC_OTRA I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
31 radio_RX_ADC_OTRB I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
32 radio_RSSI_ADC_OTR I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
33 radio_DAC_PLL_LOCK I 1 fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
34 radio_DAC_RESET O 1 fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
35 dac_spi_data O 1 fpga_0_radio_bridge_slot_2_dac_spi_data_pin
36 dac_spi_cs O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
37 dac_spi_clk O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
38 user_EEPROM_IO_T I 1 eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
39 user_EEPROM_IO_O I 1 eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
40 user_EEPROM_IO_I O 1 eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
41 user_ADC_I O 1 radio_bridge_slot_2_user_ADC_I
42 user_ADC_Q O 1 radio_bridge_slot_2_user_ADC_Q
43 user_DAC_I I 1 radio_bridge_slot_2_user_DAC_I
44 user_DAC_Q I 1 radio_bridge_slot_2_user_DAC_Q
45 user_TxModelStart O 1 radio2_txStart
46 user_RSSI_ADC_clk I 1 rssi_clk_out
47 user_RSSI_ADC_D O 1 radio_bridge_slot_2_user_RSSI_ADC_D
48 user_RxHP_external I 1 agc_rxhp_b
49 user_RxBB_gain I 1 agc_g_bb_b
50 user_RxRF_gain I 1 agc_g_rf_b
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD TARGET WARP_RC2RB_V1 radio_controller_0_RC2RB_RAD2 radio_controller_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_bridge_slot_3   WARP Radio Board Bridge Core
Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards.

IP Specs
Core Version
radio_bridge 1.30.a


radio_bridge_slot_3 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 converter_clock_in I 1 clk_40_0000MHz
1 converter_clock_out O 1 fpga_0_radio_bridge_slot_3_converter_clock_out_pin
2 radio_RSSI_ADC_clk O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
3 radio_DAC_I O 1 fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
4 radio_DAC_Q O 1 fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
5 radio_ADC_I I 1 fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
6 radio_ADC_Q I 1 fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
7 radio_B O 1 fpga_0_radio_bridge_slot_3_radio_B_pin
8 radio_ANTSW O 1 fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
9 radio_LED O 1 fpga_0_radio_bridge_slot_3_radio_LED_pin
10 radio_DIPSW I 1 fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
11 radio_RSSI_ADC_D I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
12 radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
13 radio_spi_clk O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
14 radio_spi_data O 1 fpga_0_radio_bridge_slot_3_radio_spi_data_pin
15 radio_spi_cs O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
16 radio_SHDN O 1 fpga_0_radio_bridge_slot_3_radio_SHDN_pin
17 radio_TxEn O 1 fpga_0_radio_bridge_slot_3_radio_TxEn_pin
18 radio_RxEn O 1 fpga_0_radio_bridge_slot_3_radio_RxEn_pin
19 radio_RxHP O 1 fpga_0_radio_bridge_slot_3_radio_RxHP_pin
20 radio_24PA O 1 fpga_0_radio_bridge_slot_3_radio_24PA_pin
21 radio_5PA O 1 fpga_0_radio_bridge_slot_3_radio_5PA_pin
22 radio_RX_ADC_DCS O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
23 radio_RX_ADC_DFS O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
24 radio_RX_ADC_PWDNA O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
25 radio_RX_ADC_PWDNB O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
26 radio_RSSI_ADC_CLAMP O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
27 radio_RSSI_ADC_HIZ O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
28 radio_RSSI_ADC_SLEEP O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
29 radio_LD I 1 fpga_0_radio_bridge_slot_3_radio_LD_pin
30 radio_RX_ADC_OTRA I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
31 radio_RX_ADC_OTRB I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
32 radio_RSSI_ADC_OTR I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
33 radio_DAC_PLL_LOCK I 1 fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
34 radio_DAC_RESET O 1 fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
35 dac_spi_data O 1 fpga_0_radio_bridge_slot_3_dac_spi_data_pin
36 dac_spi_cs O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
37 dac_spi_clk O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
38 user_EEPROM_IO_T I 1 eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
39 user_EEPROM_IO_O I 1 eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
40 user_EEPROM_IO_I O 1 eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
41 user_ADC_I O 1 radio_bridge_slot_3_user_ADC_I
42 user_ADC_Q O 1 radio_bridge_slot_3_user_ADC_Q
43 user_DAC_I I 1 radio_bridge_slot_3_user_DAC_I
44 user_DAC_Q I 1 radio_bridge_slot_3_user_DAC_Q
45 user_TxModelStart O 1 radio3_txStart
46 user_RSSI_ADC_clk I 1 rssi_clk_out
47 user_RSSI_ADC_D O 1 radio_bridge_slot_3_user_RSSI_ADC_D
48 user_RxHP_external I 1 agc_rxhp_c
49 user_RxBB_gain I 1 agc_g_bb_c
50 user_RxRF_gain I 1 agc_g_rf_c
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD TARGET WARP_RC2RB_V1 radio_controller_0_RC2RB_RAD3 radio_controller_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2p
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


radio_controller_0   WARP Radio Controller (PLB46)


IP Specs
Core Version
radio_controller 1.30.a


radio_controller_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
RC2RB_RAD2 INITIATOR WARP_RC2RB_V1 radio_controller_0_RC2RB_RAD2 radio_bridge_slot_2
RC2RB_RAD3 INITIATOR WARP_RC2RB_V1 radio_controller_0_RC2RB_RAD3 radio_bridge_slot_3
SPLB SLAVE PLBV46 plb_v46_40MHz 2 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xCAC00000
C_HIGHADDR 0xCAC0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 128
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_SMALLEST_MASTER 32
C_SPLB_CLK_PERIOD_PS 10000
C_FAMILY virtex4
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


rs232_db9   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.02.a IP


rs232_db9 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_rs232_db9_RX_pin
1 TX O 1 fpga_0_rs232_db9_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84020000
C_HIGHADDR 0x8402FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 57600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


rs232_usb   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.02.a IP


rs232_usb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_rs232_usb_RX_pin
1 TX O 1 fpga_0_rs232_usb_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84000000
C_HIGHADDR 0x8400FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 57600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


warplab_mimo_4x4_agc_plbw_0


IP Specs
Core Version
warplab_mimo_4x4_agc_plbw 2.00.a


warplab_mimo_4x4_agc_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 sysgen_clk I 1 clk_40_0000MHz
1 rxhp_c O 1 agc_rxhp_c
2 rxhp_b O 1 agc_rxhp_b
3 g_rf_c O 1 agc_g_rf_c
4 g_rf_b O 1 agc_g_rf_b
5 g_bb_c O 1 agc_g_bb_c
6 g_bb_b O 1 agc_g_bb_b
7 agc_done O 1 agc_is_done
8 rssi_in_d I 1 net_gnd
9 rssi_in_c I 1 radio_bridge_slot_3_user_RSSI_ADC_D
10 rssi_in_b I 1 radio_bridge_slot_2_user_RSSI_ADC_D
11 rssi_in_a I 1 net_gnd
12 reset_in I 1 net_gnd
13 q_in_d I 1 net_gnd
14 q_in_c I 1 radio_bridge_slot_3_user_ADC_Q
15 q_in_b I 1 radio_bridge_slot_2_user_ADC_Q
16 q_in_a I 1 net_gnd
17 packet_in I 1 net_gnd
18 mreset_in I 1 net_gnd
19 i_in_d I 1 net_gnd
20 i_in_c I 1 radio_bridge_slot_3_user_ADC_I
21 i_in_b I 1 radio_bridge_slot_2_user_ADC_I
22 i_in_a I 1 net_gnd
23 i_out_a O 1 dc_filtered_i_a
24 i_out_b O 1 dc_filtered_i_b
25 i_out_c O 1 dc_filtered_i_c
26 i_out_d O 1 dc_filtered_i_d
27 q_out_a O 1 dc_filtered_q_a
28 q_out_b O 1 dc_filtered_q_b
29 q_out_c O 1 dc_filtered_q_c
30 q_out_d O 1 dc_filtered_q_d
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb_v46_40MHz 2 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0xC4A00000
C_HIGHADDR 0xC4A0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_MEMMAP_GBB_A 0x844
C_MEMMAP_GBB_A_N_BITS 5
C_MEMMAP_GBB_A_BIN_PT 0
C_MEMMAP_GBB_B 0x848
C_MEMMAP_GBB_B_N_BITS 5
C_MEMMAP_GBB_B_BIN_PT 0
C_MEMMAP_GBB_C 0x84C
C_MEMMAP_GBB_C_N_BITS 5
C_MEMMAP_GBB_C_BIN_PT 0
C_MEMMAP_GBB_D 0x850
C_MEMMAP_GBB_D_N_BITS 5
C_MEMMAP_GBB_D_BIN_PT 0
C_MEMMAP_GRF_A 0x854
C_MEMMAP_GRF_A_N_BITS 2
C_MEMMAP_GRF_A_BIN_PT 0
C_MEMMAP_GRF_B 0x858
C_MEMMAP_GRF_B_N_BITS 2
C_MEMMAP_GRF_B_BIN_PT 0
C_MEMMAP_GRF_C 0x85C
C_MEMMAP_GRF_C_N_BITS 2
C_MEMMAP_GRF_C_BIN_PT 0
C_MEMMAP_GRF_D 0x860
C_MEMMAP_GRF_D_N_BITS 2
C_MEMMAP_GRF_D_BIN_PT 0
C_MEMMAP_ADJ 0x800
C_MEMMAP_ADJ_N_BITS 16
C_MEMMAP_ADJ_BIN_PT 0
C_MEMMAP_AGC_EN 0x804
C_MEMMAP_AGC_EN_N_BITS 1
C_MEMMAP_AGC_EN_BIN_PT 0
C_MEMMAP_AGC_TRIGGER_DELAY 0x808
C_MEMMAP_AGC_TRIGGER_DELAY_N_BITS 9
C_MEMMAP_AGC_TRIGGER_DELAY_BIN_PT 0
 
Name Value
C_MEMMAP_AVG_LEN 0x80C
C_MEMMAP_AVG_LEN_N_BITS 16
C_MEMMAP_AVG_LEN_BIN_PT 0
C_MEMMAP_BITS 0x810
C_MEMMAP_BITS_N_BITS 10
C_MEMMAP_BITS_BIN_PT 0
C_MEMMAP_DCO_TIMING 0x814
C_MEMMAP_DCO_TIMING_N_BITS 32
C_MEMMAP_DCO_TIMING_BIN_PT 0
C_MEMMAP_GBB_INIT 0x818
C_MEMMAP_GBB_INIT_N_BITS 16
C_MEMMAP_GBB_INIT_BIN_PT 0
C_MEMMAP_MRESET_IN 0x81C
C_MEMMAP_MRESET_IN_N_BITS 1
C_MEMMAP_MRESET_IN_BIN_PT 0
C_MEMMAP_PACKET_IN 0x820
C_MEMMAP_PACKET_IN_N_BITS 1
C_MEMMAP_PACKET_IN_BIN_PT 0
C_MEMMAP_RADIO1_AGC_EN 0x824
C_MEMMAP_RADIO1_AGC_EN_N_BITS 1
C_MEMMAP_RADIO1_AGC_EN_BIN_PT 0
C_MEMMAP_RADIO2_AGC_EN 0x828
C_MEMMAP_RADIO2_AGC_EN_N_BITS 1
C_MEMMAP_RADIO2_AGC_EN_BIN_PT 0
C_MEMMAP_RADIO3_AGC_EN 0x82C
C_MEMMAP_RADIO3_AGC_EN_N_BITS 1
C_MEMMAP_RADIO3_AGC_EN_BIN_PT 0
C_MEMMAP_RADIO4_AGC_EN 0x830
C_MEMMAP_RADIO4_AGC_EN_N_BITS 1
C_MEMMAP_RADIO4_AGC_EN_BIN_PT 0
C_MEMMAP_SRESET_IN 0x834
C_MEMMAP_SRESET_IN_N_BITS 1
C_MEMMAP_SRESET_IN_BIN_PT 0
C_MEMMAP_T_DB 0x838
C_MEMMAP_T_DB_N_BITS 16
C_MEMMAP_T_DB_BIN_PT 0
C_MEMMAP_THRESHOLDS 0x83C
C_MEMMAP_THRESHOLDS_N_BITS 32
C_MEMMAP_THRESHOLDS_BIN_PT 0
C_MEMMAP_TIMING 0x840
C_MEMMAP_TIMING_N_BITS 32
C_MEMMAP_TIMING_BIN_PT 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


warplab_mimo_4x4_plbw_0


IP Specs
Core Version
warplab_mimo_4x4_plbw 1.04.a


warplab_mimo_4x4_plbw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 sysgen_clk I 1 clk_40_0000MHz
1 radio1_adc_i I 1 net_gnd
2 radio1_adc_q I 1 net_gnd
3 radio1_adc_i_otr I 1 net_gnd
4 radio1_adc_q_otr I 1 net_gnd
5 radio2_adc_i I 1 radio_bridge_slot_2_user_ADC_I
6 radio2_adc_q I 1 radio_bridge_slot_2_user_ADC_Q
7 radio2_adc_i_otr I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
8 radio2_adc_q_otr I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
9 startcapture I 1 net_gnd
10 StartTx I 1 net_gnd
11 StopTx I 1 net_gnd
12 radio2_dac_i O 1 radio_bridge_slot_2_user_DAC_I
13 radio2_dac_q O 1 radio_bridge_slot_2_user_DAC_Q
14 rssi_adc_clk O 1 rssi_clk_out
15 debug_capturing O 1 rxrun
16 debug_transmitting O 1 txrun
17 debug_agc_done O 1 agcsetdone
18 radio3_adc_i I 1 radio_bridge_slot_3_user_ADC_I
19 radio3_adc_i_otr I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
20 radio3_adc_q I 1 radio_bridge_slot_3_user_ADC_Q
21 radio3_adc_q_otr I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
22 radio3_dac_i O 1 radio_bridge_slot_3_user_DAC_I
23 radio3_dac_q O 1 radio_bridge_slot_3_user_DAC_Q
24 radio4_adc_i I 1 net_gnd
25 radio4_adc_q I 1 net_gnd
26 radio4_adc_i_otr I 1 net_gnd
27 radio4_adc_q_otr I 1 net_gnd
28 radio1_rssi I 1 net_gnd
29 radio2_rssi I 1 radio_bridge_slot_2_user_RSSI_ADC_D
30 radio3_rssi I 1 radio_bridge_slot_3_user_RSSI_ADC_D
31 radio4_rssi I 1 net_gnd
32 agc_done I 1 agc_is_done
33 fromagc_radio1_i I 1 dc_filtered_i_a
34 fromagc_radio1_q I 1 dc_filtered_q_a
35 fromagc_radio2_i I 1 dc_filtered_i_b
36 fromagc_radio2_q I 1 dc_filtered_q_b
37 fromagc_radio3_i I 1 dc_filtered_i_c
38 fromagc_radio3_q I 1 dc_filtered_q_c
39 fromagc_radio4_i I 1 dc_filtered_i_d
40 fromagc_radio4_q I 1 dc_filtered_q_d
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x83800000
C_HIGHADDR 0x83BFFFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_MEMMAP_AGCDONEADDR 0x200054
C_MEMMAP_AGCDONEADDR_N_BITS 14
C_MEMMAP_AGCDONEADDR_BIN_PT 0
C_MEMMAP_CAPTUREDONE 0x200058
C_MEMMAP_CAPTUREDONE_N_BITS 1
C_MEMMAP_CAPTUREDONE_BIN_PT 0
C_MEMMAP_RADIO1AGCDONERSSI 0x20005C
C_MEMMAP_RADIO1AGCDONERSSI_N_BITS 10
C_MEMMAP_RADIO1AGCDONERSSI_BIN_PT 0
C_MEMMAP_RADIO2AGCDONERSSI 0x200060
C_MEMMAP_RADIO2AGCDONERSSI_N_BITS 10
C_MEMMAP_RADIO2AGCDONERSSI_BIN_PT 0
C_MEMMAP_RADIO3AGCDONERSSI 0x200064
C_MEMMAP_RADIO3AGCDONERSSI_N_BITS 10
C_MEMMAP_RADIO3AGCDONERSSI_BIN_PT 0
C_MEMMAP_RADIO4AGCDONERSSI 0x200068
C_MEMMAP_RADIO4AGCDONERSSI_N_BITS 10
C_MEMMAP_RADIO4AGCDONERSSI_BIN_PT 0
C_MEMMAP_DCO_EN_SEL 0x200000
C_MEMMAP_DCO_EN_SEL_N_BITS 1
C_MEMMAP_DCO_EN_SEL_BIN_PT 0
C_MEMMAP_DEBUGRX1BUFFERS 0x200004
C_MEMMAP_DEBUGRX1BUFFERS_N_BITS 1
C_MEMMAP_DEBUGRX1BUFFERS_BIN_PT 0
C_MEMMAP_DEBUGRX2BUFFERS 0x200008
C_MEMMAP_DEBUGRX2BUFFERS_N_BITS 1
C_MEMMAP_DEBUGRX2BUFFERS_BIN_PT 0
C_MEMMAP_DEBUGRX3BUFFERS 0x20000C
C_MEMMAP_DEBUGRX3BUFFERS_N_BITS 1
C_MEMMAP_DEBUGRX3BUFFERS_BIN_PT 0
C_MEMMAP_DEBUGRX4BUFFERS 0x200010
C_MEMMAP_DEBUGRX4BUFFERS_N_BITS 1
C_MEMMAP_DEBUGRX4BUFFERS_BIN_PT 0
C_MEMMAP_MGC_AGC_SEL 0x200014
C_MEMMAP_MGC_AGC_SEL_N_BITS 1
C_MEMMAP_MGC_AGC_SEL_BIN_PT 0
C_MEMMAP_RADIO1RXBUFF_RXEN 0x200018
C_MEMMAP_RADIO1RXBUFF_RXEN_N_BITS 1
C_MEMMAP_RADIO1RXBUFF_RXEN_BIN_PT 0
C_MEMMAP_RADIO1TXBUFF_TXEN 0x20001C
C_MEMMAP_RADIO1TXBUFF_TXEN_N_BITS 1
C_MEMMAP_RADIO1TXBUFF_TXEN_BIN_PT 0
C_MEMMAP_RADIO2RXBUFF_RXEN 0x200020
C_MEMMAP_RADIO2RXBUFF_RXEN_N_BITS 1
C_MEMMAP_RADIO2RXBUFF_RXEN_BIN_PT 0
C_MEMMAP_RADIO2TXBUFF_TXEN 0x200024
C_MEMMAP_RADIO2TXBUFF_TXEN_N_BITS 1
C_MEMMAP_RADIO2TXBUFF_TXEN_BIN_PT 0
C_MEMMAP_RADIO3RXBUFF_RXEN 0x200028
C_MEMMAP_RADIO3RXBUFF_RXEN_N_BITS 1
C_MEMMAP_RADIO3RXBUFF_RXEN_BIN_PT 0
C_MEMMAP_RADIO3TXBUFF_TXEN 0x20002C
C_MEMMAP_RADIO3TXBUFF_TXEN_N_BITS 1
C_MEMMAP_RADIO3TXBUFF_TXEN_BIN_PT 0
C_MEMMAP_RADIO4RXBUFF_RXEN 0x200030
C_MEMMAP_RADIO4RXBUFF_RXEN_N_BITS 1
C_MEMMAP_RADIO4RXBUFF_RXEN_BIN_PT 0
C_MEMMAP_RADIO4TXBUFF_TXEN 0x200034
C_MEMMAP_RADIO4TXBUFF_TXEN_N_BITS 1
C_MEMMAP_RADIO4TXBUFF_TXEN_BIN_PT 0
 
Name Value
C_MEMMAP_STARTCAPTURE 0x200038
C_MEMMAP_STARTCAPTURE_N_BITS 1
C_MEMMAP_STARTCAPTURE_BIN_PT 0
C_MEMMAP_STARTTX 0x20003C
C_MEMMAP_STARTTX_N_BITS 1
C_MEMMAP_STARTTX_BIN_PT 0
C_MEMMAP_STOPTX 0x200040
C_MEMMAP_STOPTX_N_BITS 1
C_MEMMAP_STOPTX_BIN_PT 0
C_MEMMAP_TRANSMODE 0x200044
C_MEMMAP_TRANSMODE_N_BITS 1
C_MEMMAP_TRANSMODE_BIN_PT 0
C_MEMMAP_TXDELAY 0x200048
C_MEMMAP_TXDELAY_N_BITS 14
C_MEMMAP_TXDELAY_BIN_PT 0
C_MEMMAP_TXLENGTH 0x20004C
C_MEMMAP_TXLENGTH_N_BITS 14
C_MEMMAP_TXLENGTH_BIN_PT 0
C_MEMMAP_STARTTXRX 0x200050
C_MEMMAP_STARTTXRX_N_BITS 1
C_MEMMAP_STARTTXRX_BIN_PT 0
C_MEMMAP_RXBUFF_RADIO1 0x000000
C_MEMMAP_RXBUFF_RADIO1_N_BITS 32
C_MEMMAP_RXBUFF_RADIO1_BIN_PT 0
C_MEMMAP_RXBUFF_RADIO1_DEPTH 16384
C_MEMMAP_RXBUFF_RADIO2 0x010000
C_MEMMAP_RXBUFF_RADIO2_N_BITS 32
C_MEMMAP_RXBUFF_RADIO2_BIN_PT 0
C_MEMMAP_RXBUFF_RADIO2_DEPTH 16384
C_MEMMAP_RXBUFF_RADIO3 0x020000
C_MEMMAP_RXBUFF_RADIO3_N_BITS 32
C_MEMMAP_RXBUFF_RADIO3_BIN_PT 0
C_MEMMAP_RXBUFF_RADIO3_DEPTH 16384
C_MEMMAP_RXBUFF_RADIO4 0x030000
C_MEMMAP_RXBUFF_RADIO4_N_BITS 32
C_MEMMAP_RXBUFF_RADIO4_BIN_PT 0
C_MEMMAP_RXBUFF_RADIO4_DEPTH 16384
C_MEMMAP_TXBUFF_RADIO1 0x040000
C_MEMMAP_TXBUFF_RADIO1_N_BITS 32
C_MEMMAP_TXBUFF_RADIO1_BIN_PT 0
C_MEMMAP_TXBUFF_RADIO1_DEPTH 16384
C_MEMMAP_TXBUFF_RADIO2 0x050000
C_MEMMAP_TXBUFF_RADIO2_N_BITS 32
C_MEMMAP_TXBUFF_RADIO2_BIN_PT 0
C_MEMMAP_TXBUFF_RADIO2_DEPTH 16384
C_MEMMAP_TXBUFF_RADIO3 0x060000
C_MEMMAP_TXBUFF_RADIO3_N_BITS 32
C_MEMMAP_TXBUFF_RADIO3_BIN_PT 0
C_MEMMAP_TXBUFF_RADIO3_DEPTH 16384
C_MEMMAP_TXBUFF_RADIO4 0x070000
C_MEMMAP_TXBUFF_RADIO4_N_BITS 32
C_MEMMAP_TXBUFF_RADIO4_BIN_PT 0
C_MEMMAP_TXBUFF_RADIO4_DEPTH 16384
C_MEMMAP_RSSIBUFF_RADIO1 0x080000
C_MEMMAP_RSSIBUFF_RADIO1_N_BITS 32
C_MEMMAP_RSSIBUFF_RADIO1_BIN_PT 0
C_MEMMAP_RSSIBUFF_RADIO1_DEPTH 2048
C_MEMMAP_RSSIBUFF_RADIO2 0x082000
C_MEMMAP_RSSIBUFF_RADIO2_N_BITS 32
C_MEMMAP_RSSIBUFF_RADIO2_BIN_PT 0
C_MEMMAP_RSSIBUFF_RADIO2_DEPTH 2048
C_MEMMAP_RSSIBUFF_RADIO3 0x084000
C_MEMMAP_RSSIBUFF_RADIO3_N_BITS 32
C_MEMMAP_RSSIBUFF_RADIO3_BIN_PT 0
C_MEMMAP_RSSIBUFF_RADIO3_DEPTH 2048
C_MEMMAP_RSSIBUFF_RADIO4 0x086000
C_MEMMAP_RSSIBUFF_RADIO4_N_BITS 32
C_MEMMAP_RSSIBUFF_RADIO4_BIN_PT 0
C_MEMMAP_RSSIBUFF_RADIO4_DEPTH 2048
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_central_dma_0   XPS Central DMA Controller
Simple Direct Memory Access (DMA) services for PLBV46

IP Specs
Core Version Documentation
xps_central_dma 2.03.a IP


xps_central_dma_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MPLB MASTER PLBV46 plb 11 Peripherals.
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FIFO_DEPTH 8
C_RD_BURST_SIZE 8
C_WR_BURST_SIZE 8
C_BASEADDR 0x80200000
C_HIGHADDR 0x8020FFFF
C_SPLB_DWIDTH 32
C_SPLB_AWIDTH 32
C_SPLB_NUM_MASTERS 1
 
Name Value
C_SPLB_MID_WIDTH 1
C_SPLB_P2P 0
C_SPLB_NATIVE_DWIDTH 32
C_MPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MPLB_AWIDTH 32
C_MPLB_DWIDTH 32
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_timer_0   XPS Timer/Counter
Timer counter with PLBV46 interface

IP Specs
Core Version Documentation
xps_timer 1.02.a IP


xps_timer_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 plb 11 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_COUNT_WIDTH 32
C_ONE_TIMER_ONLY 0
C_TRIG0_ASSERT 1
C_TRIG1_ASSERT 1
C_GEN0_ASSERT 1
C_GEN1_ASSERT 1
C_BASEADDR 0x83C00000
 
Name Value
C_HIGHADDR 0x83C0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
C_SPLB_NUM_MASTERS 8
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOP

clk_board_config   WARP Clock Board Configuration Core
Configures the Clock Board after FPGA configuration- requied to use the Clock Board oscillators as the master FPGA clock, sampling clock for Radio Boards and RF refence clock for Radio Boards.

IP Specs
Core Version
clock_board_config 1.05.a


clk_board_config IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 sys_clk I 1 fpga_0_clk_board_config_sys_clk_pin
1 sys_rst I 1 net_gnd
2 cfg_radio_dat_out O 1 fpga_0_clk_board_config_cfg_radio_dat_out_pin
3 cfg_radio_csb_out O 1 fpga_0_clk_board_config_cfg_radio_csb_out_pin
4 cfg_radio_en_out O 1 fpga_0_clk_board_config_cfg_radio_en_out_pin
5 cfg_radio_clk_out O 1 fpga_0_clk_board_config_cfg_radio_clk_out_pin
6 cfg_logic_dat_out O 1 fpga_0_clk_board_config_cfg_logic_dat_out_pin
7 cfg_logic_csb_out O 1 fpga_0_clk_board_config_cfg_logic_csb_out_pin
8 cfg_logic_en_out O 1 fpga_0_clk_board_config_cfg_logic_en_out_pin
9 cfg_logic_clk_out O 1 fpga_0_clk_board_config_cfg_logic_clk_out_pin
10 radio_clk_src_sel I 1 net_gnd
11 logic_clk_src_sel I 1 net_gnd
12 config_invalid O 1 clk_board_config_config_invalid


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
radio_clk_source_sel_mode 0
logic_clk_source_sel_mode 0
fpga_radio_clk_source 0
fpga_logic_clk_source 0
radio_clk_out4_mode 0x01FF
radio_clk_out5_mode 0x1EFF
radio_clk_out6_mode 0x1EFF
radio_clk_out7_mode 0x01FF
logic_clk_out0_mode 0x02FF
logic_clk_out1_mode 0x02FF
 
Name Value
logic_clk_out2_mode 0x08FF
logic_clk_out3_mode 0x08FF
radio_clk_forward_out_mode 0x0BFF
logic_clk_forward_out_mode 0x1FFF
sys_clk_freq_hz 0x05F5E100
scp_min_freq_hz 0x002625A0
scp_cyc_leng_a 0x00000028
scp_cyc_leng_b 0x00000028
scp_cyc_leng 0x00000028
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKIN I 1 CLK_S
1 CLKOUT0 O 1 clk_125_0000MHz
2 CLKOUT1 O 1 clk_160_0000MHzDCM0
3 CLKOUT2 O 1 clk_200_0000MHz
4 CLKOUT3 O 1 clk_40_0000MHz
5 CLKOUT4 O 1 clk_80_0000MHzDCM0
6 RST I 1 clk_board_config_config_invalid
7 LOCKED O 1 Dcm_all_locked


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 40000000
C_CLKOUT0_FREQ 125000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP NONE
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 160000000
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP DCM0
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 200000000
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 40000000
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 80000000
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP DCM0
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOP


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.