BlockDiagram

EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
0GLB fpga_0_USER_IO_GPIO_in_pin I 0:7 fpga_0_USER_IO_GPIO_in
1GLB debug O 0:2 rxrun & txrun & agcsetdone
2A fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col
3A fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs
4A fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv
5A fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk
6A fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data
7A fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er
8A fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk
9A fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n
10A fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data
11A fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en
12B fpga_0_USER_IO_GPIO2_d_out_pin O 0:17 fpga_0_USER_IO_GPIO2_d_out
13C fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk
14C fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out
15C fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out
16C fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out
17C fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out
18C fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out
19C fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out
20C fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out
21C fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out
22D sys_clk_pin I 1 dcm_clk_s  CLK 
23E fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0
24E fpga_0_Ethernet_MAC_slew1_pin O 1 net_vcc
25E fpga_0_Ethernet_MAC_slew2_pin O 1 net_vcc
26F sys_rst_pin I 1 sys_rst_s  RESET 
27G fpga_0_radio_bridge_slot_1_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_1_radio_ADC_I
28G fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_1_radio_ADC_Q
29G fpga_0_radio_bridge_slot_1_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_1_radio_DIPSW
30G fpga_0_radio_bridge_slot_1_radio_LD_pin I 1 fpga_0_radio_bridge_slot_1_radio_LD
31G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D
32G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR
33G fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA
34G fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB
35G fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK
36G fpga_0_radio_bridge_slot_1_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_1_radio_EEPROM_IO
37G fpga_0_radio_bridge_slot_1_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_1_converter_clock_out
38G fpga_0_radio_bridge_slot_1_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_1_dac_spi_clk
39G fpga_0_radio_bridge_slot_1_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_1_dac_spi_cs
40G fpga_0_radio_bridge_slot_1_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_1_dac_spi_data
41G fpga_0_radio_bridge_slot_1_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_1_radio_24PA
42G fpga_0_radio_bridge_slot_1_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_1_radio_5PA
43G fpga_0_radio_bridge_slot_1_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_1_radio_ANTSW
44G fpga_0_radio_bridge_slot_1_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_1_radio_B
45G fpga_0_radio_bridge_slot_1_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_1_radio_DAC_I
46G fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_1_radio_DAC_Q
47G fpga_0_radio_bridge_slot_1_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_1_radio_LED
48G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP
49G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ
50G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP
51G fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk
52G fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS
53G fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS
54G fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA
55G fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB
56G fpga_0_radio_bridge_slot_1_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_1_radio_RxEn
57G fpga_0_radio_bridge_slot_1_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_1_radio_RxHP
58G fpga_0_radio_bridge_slot_1_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_1_radio_SHDN
59G fpga_0_radio_bridge_slot_1_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_1_radio_TxEn
60G fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_1_radio_dac_RESET
61G fpga_0_radio_bridge_slot_1_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_1_radio_spi_clk
62G fpga_0_radio_bridge_slot_1_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_1_radio_spi_cs
63G fpga_0_radio_bridge_slot_1_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_1_radio_spi_data
64H fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_I
65H fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_Q
66H fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_2_radio_DIPSW
67H fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD
68H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D
69H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR
70H fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA
71H fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB
72H fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK
73H fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO
74H fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out
75H fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk
76H fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs
77H fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data
78H fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA
79H fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA
80H fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_2_radio_ANTSW
81H fpga_0_radio_bridge_slot_2_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_2_radio_B
82H fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_I
83H fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_Q
84H fpga_0_radio_bridge_slot_2_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_2_radio_LED
85H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP
86H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ
87H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP
88H fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
89H fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS
90H fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS
91H fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA
92H fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB
93H fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn
94H fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP
95H fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN
96H fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn
97H fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET
98H fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk
99H fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs
100H fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data
101I fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_I
102I fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_Q
103I fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_3_radio_DIPSW
104I fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD
105I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D
106I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR
107I fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA
108I fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB
109I fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK
110I fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO
111I fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out
112I fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk
113I fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs
114I fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data
115I fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA
116I fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA
117I fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_3_radio_ANTSW
118I fpga_0_radio_bridge_slot_3_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_3_radio_B
119I fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_I
120I fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_Q
121I fpga_0_radio_bridge_slot_3_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_3_radio_LED
122I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP
123I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ
124I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP
125I fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk
126I fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS
127I fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS
128I fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA
129I fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB
130I fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn
131I fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP
132I fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN
133I fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn
134I fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET
135I fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk
136I fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs
137I fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data
138J fpga_0_radio_bridge_slot_4_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_4_radio_ADC_I
139J fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_4_radio_ADC_Q
140J fpga_0_radio_bridge_slot_4_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_4_radio_DIPSW
141J fpga_0_radio_bridge_slot_4_radio_LD_pin I 1 fpga_0_radio_bridge_slot_4_radio_LD
142J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D
143J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR
144J fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA
145J fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB
146J fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK
147J fpga_0_radio_bridge_slot_4_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_4_radio_EEPROM_IO
148J fpga_0_radio_bridge_slot_4_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_4_converter_clock_out
149J fpga_0_radio_bridge_slot_4_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_4_dac_spi_clk
150J fpga_0_radio_bridge_slot_4_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_4_dac_spi_cs
151J fpga_0_radio_bridge_slot_4_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_4_dac_spi_data
152J fpga_0_radio_bridge_slot_4_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_4_radio_24PA
153J fpga_0_radio_bridge_slot_4_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_4_radio_5PA
154J fpga_0_radio_bridge_slot_4_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_4_radio_ANTSW
155J fpga_0_radio_bridge_slot_4_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_4_radio_B
156J fpga_0_radio_bridge_slot_4_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_4_radio_DAC_I
157J fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_4_radio_DAC_Q
158J fpga_0_radio_bridge_slot_4_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_4_radio_LED
159J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP
160J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ
161J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP
162J fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk
163J fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS
164J fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS
165J fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA
166J fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB
167J fpga_0_radio_bridge_slot_4_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_4_radio_RxEn
168J fpga_0_radio_bridge_slot_4_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_4_radio_RxHP
169J fpga_0_radio_bridge_slot_4_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_4_radio_SHDN
170J fpga_0_radio_bridge_slot_4_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_4_radio_TxEn
171J fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_4_radio_dac_RESET
172J fpga_0_radio_bridge_slot_4_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_4_radio_spi_clk
173J fpga_0_radio_bridge_slot_4_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_4_radio_spi_cs
174J fpga_0_radio_bridge_slot_4_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_4_radio_spi_data
175K fpga_0_rs232_RX_pin I 1 fpga_0_rs232_RX
176K fpga_0_rs232_TX_pin O 1 fpga_0_rs232_TX