EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_2_radio_ANTSW fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_2_radio_DIPSW fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD fpga_0_radio_bridge_slot_2_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_2_radio_LED fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data fpga_0_radio_bridge_slot_2_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_2_radio_B fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_I fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_2_radio_DAC_Q fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_I fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_2_radio_ADC_Q fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 1:0 fpga_0_radio_bridge_slot_3_radio_ANTSW fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 3:0 fpga_0_radio_bridge_slot_3_radio_DIPSW fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD fpga_0_radio_bridge_slot_3_radio_LED_pin O 2:0 fpga_0_radio_bridge_slot_3_radio_LED fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 9:0 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data fpga_0_radio_bridge_slot_3_radio_B_pin O 6:0 fpga_0_radio_bridge_slot_3_radio_B fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_I fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 15:0 fpga_0_radio_bridge_slot_3_radio_DAC_Q fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_I fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 13:0 fpga_0_radio_bridge_slot_3_radio_ADC_Q				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_analog_bridge_slot_4_clock_out_pin O 1 fpga_0_analog_bridge_slot_4_clock_out fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_A fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC1_B fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_A fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin O 13:0 fpga_0_analog_bridge_slot_4_analog_DAC2_B fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep fpga_0_analog_bridge_slot_4_analog_ADC_A_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_A fpga_0_analog_bridge_slot_4_analog_ADC_B_pin I 13:0 fpga_0_analog_bridge_slot_4_analog_ADC_B fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB fpga_0_analog_bridge_slot_4_analog_LED_pin O 0:2 fpga_0_analog_bridge_slot_4_analog_LED fpga_0_USER_IO_GPIO2_d_out_pin O 0:17 fpga_0_USER_IO_GPIO2_d_out fpga_0_USER_IO_GPIO_in_pin I 0:7 fpga_0_USER_IO_GPIO_in fpga_0_rs232_RX_pin I 1 fpga_0_rs232_RX fpga_0_rs232_TX_pin O 1 fpga_0_rs232_TX fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0 fpga_0_sysace_compactflash_SysACE_CLK_pin I 1 fpga_0_sysace_compactflash_SysACE_CLK fpga_0_sysace_compactflash_SysACE_MPA_pin O 6:0 fpga_0_sysace_compactflash_SysACE_MPA fpga_0_sysace_compactflash_SysACE_MPD_pin IO 15:0 fpga_0_sysace_compactflash_SysACE_MPD fpga_0_sysace_compactflash_SysACE_CEN_pin O 1 fpga_0_sysace_compactflash_SysACE_CEN fpga_0_sysace_compactflash_SysACE_OEN_pin O 1 fpga_0_sysace_compactflash_SysACE_OEN fpga_0_sysace_compactflash_SysACE_WEN_pin O 1 fpga_0_sysace_compactflash_SysACE_WEN fpga_0_sysace_compactflash_SysACE_MPIRQ_pin I 1 fpga_0_sysace_compactflash_SysACE_MPIRQ fpga_0_Ethernet_MAC_slew1_pin O 1 net_vcc fpga_0_Ethernet_MAC_slew2_pin O 1 net_vcc fpga_0_TriMode_MAC_MII_MII_TXD_0_pin O 3:0 fpga_0_TriMode_MAC_MII_MII_TXD_0 fpga_0_TriMode_MAC_MII_MII_TX_EN_0_pin O 1 fpga_0_TriMode_MAC_MII_MII_TX_EN_0 fpga_0_TriMode_MAC_MII_MII_TX_ER_0_pin O 1 fpga_0_TriMode_MAC_MII_MII_TX_ER_0 fpga_0_TriMode_MAC_MII_MII_RXD_0_pin I 3:0 fpga_0_TriMode_MAC_MII_MII_RXD_0 fpga_0_TriMode_MAC_MII_MII_RX_DV_0_pin I 1 fpga_0_TriMode_MAC_MII_MII_RX_DV_0 fpga_0_TriMode_MAC_MII_MII_RX_ER_0_pin I 1 fpga_0_TriMode_MAC_MII_MII_RX_ER_0 fpga_0_TriMode_MAC_MII_MII_TX_CLK_0_pin I 1 fpga_0_TriMode_MAC_MII_MII_TX_CLK_0 fpga_0_TriMode_MAC_MII_MII_RX_CLK_0_pin I 1 fpga_0_TriMode_MAC_MII_MII_RX_CLK_0 fpga_0_TriMode_MAC_MII_MDIO_0_pin IO 1 fpga_0_TriMode_MAC_MII_MDIO_0 fpga_0_TriMode_MAC_MII_MDC_0_pin O 1 fpga_0_TriMode_MAC_MII_MDC_0 fpga_0_TriMode_MAC_MII_TemacPhy_RST_n_pin O 1 fpga_0_TriMode_MAC_MII_TemacPhy_RST_n fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN fpga_0_SRAM0_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CE fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN fpga_0_SRAM0_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM0_ZBT_512Kx32_Mem_A fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN fpga_0_SRAM1_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CE fpga_0_SRAM1_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM1_ZBT_512Kx32_Mem_A fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ fpga_0_SRAM0_CLOCK O 1 sys_clk_s fpga_0_SRAM1_CLOCK O 1 sys_clk_s user_io_board_controller_plbw_0_sdi_pin O 1 user_io_board_controller_plbw_0_sdi user_io_board_controller_plbw_0_scl_pin O 1 user_io_board_controller_plbw_0_scl user_io_board_controller_plbw_0_resetlcd_pin O 1 user_io_board_controller_plbw_0_resetlcd user_io_board_controller_plbw_0_leds_pin O 0:7 user_io_board_controller_plbw_0_leds user_io_board_controller_plbw_0_cs_pin O 1 user_io_board_controller_plbw_0_cs user_io_board_controller_plbw_0_buzzer_pin O 1 user_io_board_controller_plbw_0_buzzer user_io_board_controller_plbw_0_dip_switch_pin I 0:3 user_io_board_controller_plbw_0_dip_switch user_io_board_controller_plbw_0_buttons_small_pin I 0:5 user_io_board_controller_plbw_0_buttons_small user_io_board_controller_plbw_0_buttons_big_pin I 0:1 user_io_board_controller_plbw_0_buttons_big user_io_board_controller_plbw_0_trackball_yscn_pin O 1 user_io_board_controller_plbw_0_trackball_yscn user_io_board_controller_plbw_0_trackball_sel1_pin O 1 user_io_board_controller_plbw_0_trackball_sel1 user_io_board_controller_plbw_0_trackball_xscn_pin O 1 user_io_board_controller_plbw_0_trackball_xscn user_io_board_controller_plbw_0_trackball_sel2_pin I 1 user_io_board_controller_plbw_0_trackball_sel2 user_io_board_controller_plbw_0_trackball_oyn_pin I 1 user_io_board_controller_plbw_0_trackball_oyn user_io_board_controller_plbw_0_trackball_oy_pin I 1 user_io_board_controller_plbw_0_trackball_oy user_io_board_controller_plbw_0_trackball_oxn_pin I 1 user_io_board_controller_plbw_0_trackball_oxn user_io_board_controller_plbw_0_trackball_ox_pin I 1 user_io_board_controller_plbw_0_trackball_ox sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET  debug O 0:8 debug_tx_pktrunning & debug_rx_payload & rssi_pkt_detect_plbw_0_rssi_pkt_det_out & rx_int_goodpkt & rx_int_badpkt & rx_int_goodheader & ofdm_txrx_mimo_plbw_0_rx_int_badheader & rx_pktdetreset & debug_timer0_active debug_extTxStart_pin I 1 debug_extTxStart debug_chipscopetrig_pin I 1 debug_chipscopetrig debug_GPIO_d_out_pin O 0:3 fpga_0_debug_GPIO_d_out