EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB debug O 0:9 debug_tx_pktrunning & debug_rx_payload & rssi_pkt_detect_opbw_0_rssi_pkt_det_out & rx_int_goodpkt & rx_int_badpkt & rx_pktdetreset & debug_rx_pktdone & debug_antSel & ofdm_pktDetector_mimo_opbw_0_debugbusy & ofdm_pktDetector_mimo_opbw_0_debugidledifs 1GLB fpga_0_Ethernet_MAC_slew1_pin O 1 net_vcc 2GLB fpga_0_Ethernet_MAC_slew2_pin O 1 net_vcc 3GLB fpga_0_SRAM0_CLOCK O 1 sys_clk_s 4GLB fpga_0_SRAM1_CLOCK O 1 sys_clk_s 5A fpga_0_DIPSWs_4Bit_GPIO_in_pin I 0:3 fpga_0_DIPSWs_4Bit_GPIO_in 6B fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col 7B fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs 8B fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv 9B fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk 10B fpga_0_Ethernet_MAC_PHY_rx_data_pin I 0:3 fpga_0_Ethernet_MAC_PHY_rx_data 11B fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er 12B fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk 13B fpga_0_Ethernet_MAC_PHY_Mii_clk_pin IO 1 fpga_0_Ethernet_MAC_PHY_Mii_clk 14B fpga_0_Ethernet_MAC_PHY_Mii_data_pin IO 1 fpga_0_Ethernet_MAC_PHY_Mii_data 15B fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n 16B fpga_0_Ethernet_MAC_PHY_tx_data_pin O 0:3 fpga_0_Ethernet_MAC_PHY_tx_data 17B fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en 18B fpga_0_Ethernet_MAC_PHY_tx_er_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_er 19C fpga_0_LED_7SEGMENT_GPIO_d_out_pin O 0:6 fpga_0_LED_7SEGMENT_GPIO_d_out 20D fpga_0_LED_7SEGMENT_1_GPIO_d_out_pin O 0:6 fpga_0_LED_7SEGMENT_1_GPIO_d_out 21E fpga_0_LEDs_4Bit_GPIO_d_out_pin O 0:3 fpga_0_LEDs_4Bit_GPIO_d_out 22F fpga_0_Push_Buttons_4bit_GPIO_in_pin I 0:3 fpga_0_Push_Buttons_4bit_GPIO_in 23G fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ 24G fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN 25G fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN 26G fpga_0_SRAM0_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CE 27G fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN 28G fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN 29G fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN 30H fpga_0_SRAM0_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM0_ZBT_512Kx32_Mem_A 31I fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ 32I fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN 33I fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN 34I fpga_0_SRAM1_ZBT_512Kx32_Mem_CE_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CE 35I fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN 36I fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN 37I fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN_pin O 1 fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN 38J fpga_0_SRAM1_ZBT_512Kx32_Mem_A_pin O 11:29 fpga_0_SRAM1_ZBT_512Kx32_Mem_A 39K fpga_0_analog_bridge_slot_4_analog_ADC_A_pin I 0:13 fpga_0_analog_bridge_slot_4_analog_ADC_A 40K fpga_0_analog_bridge_slot_4_analog_ADC_B_pin I 0:13 fpga_0_analog_bridge_slot_4_analog_ADC_B 41K fpga_0_analog_bridge_slot_4_analog_ADC_otrA_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrA 42K fpga_0_analog_bridge_slot_4_analog_ADC_otrB_pin I 1 fpga_0_analog_bridge_slot_4_analog_ADC_otrB 43K fpga_0_analog_bridge_slot_4_analog_ADC_DCS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DCS 44K fpga_0_analog_bridge_slot_4_analog_ADC_DFS_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_DFS 45K fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnA 46K fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB_pin O 1 fpga_0_analog_bridge_slot_4_analog_ADC_pdwnB 47K fpga_0_analog_bridge_slot_4_analog_DAC1_A_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC1_A 48K fpga_0_analog_bridge_slot_4_analog_DAC1_B_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC1_B 49K fpga_0_analog_bridge_slot_4_analog_DAC1_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC1_sleep 50K fpga_0_analog_bridge_slot_4_analog_DAC2_A_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC2_A 51K fpga_0_analog_bridge_slot_4_analog_DAC2_B_pin O 0:13 fpga_0_analog_bridge_slot_4_analog_DAC2_B 52K fpga_0_analog_bridge_slot_4_analog_DAC2_sleep_pin O 1 fpga_0_analog_bridge_slot_4_analog_DAC2_sleep 53K fpga_0_analog_bridge_slot_4_analog_LED_pin O 0:2 fpga_0_analog_bridge_slot_4_analog_LED 54K fpga_0_analog_bridge_slot_4_clock_out_pin O 1 fpga_0_analog_bridge_slot_4_clock_out 55L fpga_0_clk_board_config_sys_clk_pin I 1 fpga_0_clk_board_config_sys_clk 56L fpga_0_clk_board_config_cfg_logic_clk_out_pin O 1 fpga_0_clk_board_config_cfg_logic_clk_out 57L fpga_0_clk_board_config_cfg_logic_csb_out_pin O 1 fpga_0_clk_board_config_cfg_logic_csb_out 58L fpga_0_clk_board_config_cfg_logic_dat_out_pin O 1 fpga_0_clk_board_config_cfg_logic_dat_out 59L fpga_0_clk_board_config_cfg_logic_en_out_pin O 1 fpga_0_clk_board_config_cfg_logic_en_out 60L fpga_0_clk_board_config_cfg_radio_clk_out_pin O 1 fpga_0_clk_board_config_cfg_radio_clk_out 61L fpga_0_clk_board_config_cfg_radio_csb_out_pin O 1 fpga_0_clk_board_config_cfg_radio_csb_out 62L fpga_0_clk_board_config_cfg_radio_dat_out_pin O 1 fpga_0_clk_board_config_cfg_radio_dat_out 63L fpga_0_clk_board_config_cfg_radio_en_out_pin O 1 fpga_0_clk_board_config_cfg_radio_en_out 64M sys_clk_pin I 1 dcm_clk_s  CLK  65N debug_GPIO_d_out_pin O 0:3 fpga_0_debug_GPIO_d_out 66O fpga_0_eeprom_controller_DQ0_pin IO 1 fpga_0_eeprom_controller_DQ0 67P debug_chipscopetrig_pin I 1 debug_chipscopetrig 68Q fpga_0_radio_bridge_slot_2_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_I 69Q fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_2_radio_ADC_Q 70Q fpga_0_radio_bridge_slot_2_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_2_radio_DIPSW 71Q fpga_0_radio_bridge_slot_2_radio_LD_pin I 1 fpga_0_radio_bridge_slot_2_radio_LD 72Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D 73Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR 74Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 75Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB 76Q fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK 77Q fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_2_radio_EEPROM_IO 78Q fpga_0_radio_bridge_slot_2_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_2_converter_clock_out 79Q fpga_0_radio_bridge_slot_2_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_clk 80Q fpga_0_radio_bridge_slot_2_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_cs 81Q fpga_0_radio_bridge_slot_2_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_dac_spi_data 82Q fpga_0_radio_bridge_slot_2_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_24PA 83Q fpga_0_radio_bridge_slot_2_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_2_radio_5PA 84Q fpga_0_radio_bridge_slot_2_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_2_radio_ANTSW 85Q fpga_0_radio_bridge_slot_2_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_2_radio_B 86Q fpga_0_radio_bridge_slot_2_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_I 87Q fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_2_radio_DAC_Q 88Q fpga_0_radio_bridge_slot_2_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_2_radio_LED 89Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP 90Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ 91Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP 92Q fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk 93Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS 94Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS 95Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA 96Q fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB 97Q fpga_0_radio_bridge_slot_2_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxEn 98Q fpga_0_radio_bridge_slot_2_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_2_radio_RxHP 99Q fpga_0_radio_bridge_slot_2_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_2_radio_SHDN 100Q fpga_0_radio_bridge_slot_2_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_2_radio_TxEn 101Q fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_2_radio_dac_RESET 102Q fpga_0_radio_bridge_slot_2_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_clk 103Q fpga_0_radio_bridge_slot_2_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_cs 104Q fpga_0_radio_bridge_slot_2_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_2_radio_spi_data 105R fpga_0_radio_bridge_slot_3_radio_ADC_I_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_I 106R fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin I 0:13 fpga_0_radio_bridge_slot_3_radio_ADC_Q 107R fpga_0_radio_bridge_slot_3_radio_DIPSW_pin I 0:3 fpga_0_radio_bridge_slot_3_radio_DIPSW 108R fpga_0_radio_bridge_slot_3_radio_LD_pin I 1 fpga_0_radio_bridge_slot_3_radio_LD 109R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin I 0:9 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D 110R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin I 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR 111R fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA 112R fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin I 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB 113R fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin I 1 fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK 114R fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IO 1 fpga_0_radio_bridge_slot_3_radio_EEPROM_IO 115R fpga_0_radio_bridge_slot_3_converter_clock_out_pin O 1 fpga_0_radio_bridge_slot_3_converter_clock_out 116R fpga_0_radio_bridge_slot_3_dac_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_clk 117R fpga_0_radio_bridge_slot_3_dac_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_cs 118R fpga_0_radio_bridge_slot_3_dac_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_dac_spi_data 119R fpga_0_radio_bridge_slot_3_radio_24PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_24PA 120R fpga_0_radio_bridge_slot_3_radio_5PA_pin O 1 fpga_0_radio_bridge_slot_3_radio_5PA 121R fpga_0_radio_bridge_slot_3_radio_ANTSW_pin O 0:1 fpga_0_radio_bridge_slot_3_radio_ANTSW 122R fpga_0_radio_bridge_slot_3_radio_B_pin O 0:6 fpga_0_radio_bridge_slot_3_radio_B 123R fpga_0_radio_bridge_slot_3_radio_DAC_I_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_I 124R fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin O 0:15 fpga_0_radio_bridge_slot_3_radio_DAC_Q 125R fpga_0_radio_bridge_slot_3_radio_LED_pin O 0:2 fpga_0_radio_bridge_slot_3_radio_LED 126R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP 127R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ 128R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP 129R fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk 130R fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS 131R fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS 132R fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA 133R fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin O 1 fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB 134R fpga_0_radio_bridge_slot_3_radio_RxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxEn 135R fpga_0_radio_bridge_slot_3_radio_RxHP_pin O 1 fpga_0_radio_bridge_slot_3_radio_RxHP 136R fpga_0_radio_bridge_slot_3_radio_SHDN_pin O 1 fpga_0_radio_bridge_slot_3_radio_SHDN 137R fpga_0_radio_bridge_slot_3_radio_TxEn_pin O 1 fpga_0_radio_bridge_slot_3_radio_TxEn 138R fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin O 1 fpga_0_radio_bridge_slot_3_radio_dac_RESET 139R fpga_0_radio_bridge_slot_3_radio_spi_clk_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_clk 140R fpga_0_radio_bridge_slot_3_radio_spi_cs_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_cs 141R fpga_0_radio_bridge_slot_3_radio_spi_data_pin O 1 fpga_0_radio_bridge_slot_3_radio_spi_data 142S sys_rst_pin I 1 sys_rst_s  RESET  143T fpga_0_rs232_RX_pin I 1 fpga_0_rs232_RX 144T fpga_0_rs232_TX_pin O 1 fpga_0_rs232_TX 145U user_io_board_controller_opbw_0_cs_pin O 1 user_io_board_controller_opbw_0_cs 146U user_io_board_controller_opbw_0_resetlcd_pin O 1 user_io_board_controller_opbw_0_resetlcd 147U user_io_board_controller_opbw_0_scl_pin O 1 user_io_board_controller_opbw_0_scl 148U user_io_board_controller_opbw_0_sdi_pin O 1 user_io_board_controller_opbw_0_sdi