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I am using OFDM reference design 10.0. Base system is the same one but with different software platform. I am using same code for radio board initialization given in warpphy.c. It seems tht radio board in slot 2 initializes properly and orange led lits up (rx enabled) but card in slot 3 doen't initialize .. on tht orange and red led (side to side) lits up . I guess PLL is not getting locked on tht card. Board works correctly for other designs. There are few hold violations in design but none in radio controller section. Is there something that I am overlooking ??
Thanks
Gaurav
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Try changing the second argument to WarpRadio_v1_Reset to 1:
WarpRadio_v1_Reset(XPAR_RADIO_CONTROLLER_0_BASEADDR, 1)
A value of 2 is meant for when the controller is attached to an 80MHz PLB; we fixed this bug in the new warphy.c and will incorporate it in ref design v11, coming very soon.
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actually I tried that... but didn't work!! anything else that might be wrong??
thanks..
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one thing I can observe is that there is no connection to SYS_Rst port of plb_40Mhz BUS to which radio controller is connected. may that be a reason of communication failure bet PPC and cores on that BUS ?
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The usual PLB reset signal (SPLB_Rst) is connected to the radio controller. Is there another reset you see that is missing?
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I see what you were talking about- the SYS_Rst input on the 40MHz PLB itself. That could be a problem...
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yes I am talking about Reset signal going to plb_32b_40MHz core. SYS_Rst of plb0 core is connected to sys_bus_reset signal but for plb_32b_40MHz core it is floating connection..
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In hardware it got tied to ground; from system.vhd:
plb_32b_40MHz : plb_32b_40mhz_wrapper
port map (
PLB_Clk => clk_40MHz,
SYS_Rst => net_gnd0,I don't know what effect that would have in practice. I'll definitely connect it in the next ref design. But I don't know how that would cause radio 3 to lock only with some software platforms.
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I think we traced the problem to two factors:
-The clock board configuration core now disables unused outputs to reduce power consumption and noise. The outputs enabled by default are J10/J11 (radio reference) and J9/J13 (sampling reference) - see the clock board user's guide for connector labels.
-The clock board config core in OFDM reference design v10 mistakenly enables J7/J9 instead of J9/J13. This results in one radio not receiving a sampling clock. In new kits, J13 is connected to the radio in slot 3, which is why we didn't catch the bug in the SISO design (that uses radio 2 by default). The default outputs are correct in the clock config core v1.04a.
If you're just starting with a new project, I suggest using the cores that will make up reference design v11. We improved the performance of the PHY quite a bit, with lower latency (by running the Rx FFT faster) and better phase tracking. I posted a "beta" of the design to http://warp.rice.edu/bigFiles/OFDM_Refe … 11_v01.zip. The CSMA software project in this design works over the air. We're still testing the other MAC software projects (RTS/CTS especially). We'll update the reference design page with the final project soon.
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that solved the problem..
Thanks
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