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What do we need to connect two WARP boards to have the same clock ( in order to have them synchronized) ? What are the specs of the cable to use? Can we suggest where to get it from? Is there any constraints on the length of the cable? Is there anything we need other than the cable?
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You need a coaxial cable with MMCX-jacks on both ends to share clocks between WARP nodes. The clock board users guide lists the various connectors on the board used to drive/receive clock signals.
We use cables made by RF Industries. The longest cable we've used is 36" of RG-174 coax, and it works great. I suspect even longer cables would work as well. The RFI part number for a 36" RG-174 MMCX-jack to MMCX-jack cable is RFW-8727-36 (at least, it was in June when we last ordered some).
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We are connecting the External radio reference input (J2) on one board to External radio reference output (J4) on the other board. We also tried connecting External sampling clock input (J3) to External sampling clock output (J5).
Are we doing this right? Because as far as we can tell the clocks are not synchronized and we are still receiving our samples out of phase.
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In addition to connecting the clock boards, you need to modify the FPGA design to indicate which source the clock board should use for its clock inputs (see the clock board user guide for more details). In your XPS project, double-click the clock_board_config core. Here you can select 'oscillator' or 'external coax' for the two clocks (fpga_radio_clk_source is the RF carrier reference; fpga_logic_clk_source is the sampling/FPGA clock).
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We have tried doing this. These are the steps we followed:
1) We resynthesized the code in XPS for one node to be source of both radio and logic clock, and the other node source the two clocks as inputs. We generated two different bitstreams for these.
2) We connected the radio clock and the sample clocks of the two boards together with connectors.
3) Downloaded the new bitstreams on to the FPGAs and reran the experiments.
The original setup (DPSK) is working perfectly, so we know our bitstreams are ok. But QAM is getting BER of around 0.5 or more most of the time, and 0 occasionally. We modified the preamble for QAM to be [-1+j, -1+j, -1+j, 1-j, -1+j. 0, 0, 0 ....] - the original preamble for DPSK was [-1, -1, -1, 1, -1, 0, 0, 0, ...] and could not be detected occasionally with QAM. Is our approach correct?
Thank you for your response.
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In your QAM experiment, do you compensate for phase offsets between the Tx and Rx nodes? Sharing clocks will eliminate any frequency offset, but there will always be a phase difference. THe phase offset should be constant for a given experiment, as long as the boards stay powered on (the MAX2829's PLL keeps running in Tx, Rx and standby modes).
One way to verify that your nodes really are sharing clocks is to use WARPLab to send a simple signal, like a sinusoid. The Tx and Rx sinusoids should have identical frequencies but will have different phases.
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