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| 18 | |
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| 19 | #include "radio_controller_5ghz.h" |
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| 20 | |
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| 21 | |
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| 22 | |
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| 23 | |
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| 24 | |
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| 25 | |
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| 26 | |
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| 27 | |
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| 28 | |
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| 29 | |
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| 30 | |
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| 31 | void WarpRadio_v1_5AmpEnable(unsigned int radios) { |
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| 32 | |
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| 33 | RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) | (radios & RAD_5PA_MASK))); |
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| 34 | } |
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| 35 | |
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| 36 | |
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| 37 | |
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| 38 | |
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| 39 | |
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| 40 | |
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| 41 | |
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| 42 | |
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| 43 | |
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| 44 | void WarpRadio_v1_5AmpDisable(unsigned int radios) { |
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| 45 | |
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| 46 | RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~(radios & RAD_5PA_MASK))); |
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| 47 | } |
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| 48 | |
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| 49 | |
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| 50 | |
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| 78 | |
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| 80 | |
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| 81 | |
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| 82 | int WarpRadio_v1_SetCenterFreq5GHz(char freqset, unsigned int radios) { |
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| 83 | |
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| 84 | RADIO_CONTROLLER_mWriteSlaveReg7((volatile)radio_controller_baseaddr, (SLAVEMASK & radios)); |
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| 85 | |
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| 86 | unsigned int reg3; |
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| 87 | unsigned int reg4; |
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| 88 | unsigned int reg5; |
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| 89 | int band5; |
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| 90 | int retval; |
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| 91 | unsigned int mask5gl1 = 0x0001; |
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| 92 | unsigned int mask5gl2 = 0xFFBF; |
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| 93 | unsigned int mask5gh = 0x0041; |
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| 94 | |
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| 95 | switch(freqset) { |
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| 96 | case(1) : { |
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| 97 | reg3 = 0x30CF3; |
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| 98 | reg4 = 0x0CCC4; |
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| 99 | retval = 5180; |
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| 100 | band5 = 1; |
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| 101 | break; |
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| 102 | } |
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| 103 | case(2) : { |
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| 104 | reg3 = 0x00D03; |
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| 105 | reg4 = 0x00004; |
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| 106 | retval = 5200; |
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| 107 | band5 = 1; |
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| 108 | break; |
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| 109 | } |
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| 110 | case(3) : { |
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| 111 | reg3 = 0x00D03; |
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| 112 | reg4 = 0x33334; |
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| 113 | retval = 5220; |
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| 114 | band5 = 1; |
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| 115 | break; |
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| 116 | } |
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| 117 | case(4) : { |
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| 118 | reg3 = 0x10D13; |
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| 119 | reg4 = 0x26664; |
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| 120 | retval = 5240; |
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| 121 | band5 = 1; |
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| 122 | break; |
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| 123 | } |
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| 124 | case(5) : { |
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| 125 | reg3 = 0x20D23; |
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| 126 | reg4 = 0x19994; |
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| 127 | retval = 5260; |
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| 128 | band5 = 1; |
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| 129 | break; |
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| 130 | } |
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| 131 | case(6) : { |
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| 132 | reg3 = 0x30D33; |
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| 133 | reg4 = 0x0CCC4; |
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| 134 | retval = 5280; |
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| 135 | band5 = 1; |
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| 136 | break; |
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| 137 | } |
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| 138 | case(7) : { |
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| 139 | reg3 = 0x00D43; |
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| 140 | reg4 = 0x00004; |
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| 141 | retval = 5300; |
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| 142 | band5 = 1; |
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| 143 | break; |
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| 144 | } |
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| 145 | case(8) : { |
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| 146 | reg3 = 0x00D43; |
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| 147 | reg4 = 0x33334; |
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| 148 | retval = 5320; |
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| 149 | band5 = 1; |
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| 150 | break; |
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| 151 | } |
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| 152 | case(9) : { |
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| 153 | reg3 = 0x00DC3; |
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| 154 | reg4 = 0x00004; |
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| 155 | retval = 5500; |
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| 156 | band5 = 2; |
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| 157 | break; |
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| 158 | } |
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| 159 | case(10) : { |
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| 160 | reg3 = 0x00DC3; |
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| 161 | reg4 = 0x33334; |
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| 162 | retval = 5520; |
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| 163 | band5 = 2; |
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| 164 | break; |
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| 165 | } |
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| 166 | case(11) : { |
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| 167 | reg3 = 0x10DD3; |
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| 168 | reg4 = 0x26664; |
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| 169 | retval = 5540; |
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| 170 | band5 = 2; |
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| 171 | break; |
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| 172 | } |
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| 173 | case(12) : { |
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| 174 | reg3 = 0x20DE3; |
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| 175 | reg4 = 0x19994; |
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| 176 | retval = 5560; |
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| 177 | band5 = 2; |
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| 178 | break; |
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| 179 | } |
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| 180 | case(13) : { |
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| 181 | reg3 = 0x30DF3; |
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| 182 | reg4 = 0x0CCC4; |
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| 183 | retval = 5580; |
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| 184 | band5 = 2; |
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| 185 | break; |
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| 186 | } |
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| 187 | case(14) : { |
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| 188 | reg3 = 0x00E03; |
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| 189 | reg4 = 0x00004; |
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| 190 | retval = 5600; |
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| 191 | band5 = 2; |
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| 192 | break; |
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| 193 | } |
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| 194 | case(15) : { |
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| 195 | reg3 = 0x00E03; |
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| 196 | reg4 = 0x33334; |
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| 197 | retval = 5620; |
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| 198 | band5 = 2; |
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| 199 | break; |
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| 200 | } |
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| 201 | case(16) : { |
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| 202 | reg3 = 0x10E13; |
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| 203 | reg4 = 0x26664; |
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| 204 | retval = 5640; |
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| 205 | band5 = 2; |
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| 206 | break; |
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| 207 | } |
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| 208 | case(17) : { |
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| 209 | reg3 = 0x20E23; |
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| 210 | reg4 = 0x19994; |
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| 211 | retval = 5660; |
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| 212 | band5 = 2; |
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| 213 | break; |
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| 214 | } |
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| 215 | case(18) : { |
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| 216 | reg3 = 0x30E33; |
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| 217 | reg4 = 0x0CCC4; |
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| 218 | retval = 5680; |
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| 219 | band5 = 2; |
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| 220 | break; |
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| 221 | } |
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| 222 | case(19) : { |
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| 223 | reg3 = 0x00E43; |
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| 224 | reg4 = 0x00004; |
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| 225 | retval = 5700; |
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| 226 | band5 = 2; |
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| 227 | break; |
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| 228 | } |
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| 229 | case(20) : { |
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| 230 | reg3 = 0x00E53; |
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| 231 | reg4 = 0x33334; |
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| 232 | retval = 5745; |
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| 233 | band5 = 2; |
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| 234 | break; |
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| 235 | } |
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| 236 | case(21) : { |
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| 237 | reg3 = 0x10E63; |
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| 238 | reg4 = 0x26664; |
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| 239 | retval = 5765; |
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| 240 | band5 = 2; |
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| 241 | break; |
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| 242 | } |
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| 243 | case(22) : { |
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| 244 | reg3 = 0x20E73; |
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| 245 | reg4 = 0x19994; |
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| 246 | retval = 5785; |
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| 247 | band5 = 2; |
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| 248 | break; |
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| 249 | } |
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| 250 | case(23) : { |
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| 251 | reg3 = 0x30E83; |
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| 252 | reg4 = 0x0CCC4; |
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| 253 | retval = 5805; |
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| 254 | band5 = 2; |
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| 255 | break; |
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| 256 | } |
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| 257 | default : { |
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| 258 | retval = INVALID_FREQ; |
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| 259 | } |
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| 260 | } |
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| 261 | |
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| 262 | if(retval != -1) { |
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| 263 | |
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| 264 | transmit(reg3); |
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| 265 | transmit(reg4); |
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| 266 | |
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| 267 | reg3 = reg3>>4; |
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| 268 | reg4 = reg4>>4; |
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| 269 | |
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| 270 | if (band5 == 1) { |
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| 271 | if((radios & RAD1MASK) > 0) { |
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| 272 | |
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| 273 | reg5 = REG_RAD1_BAND_SELECT | mask5gl1; |
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| 274 | reg5 = reg5 & mask5gl2; |
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| 275 | |
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| 276 | transRadio(0x0001, ((reg5<<4)+0x0005)); |
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| 277 | transRadio(0x0001, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 278 | transRadio(0x0001, ((reg5<<4)+0x0005)); |
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| 279 | |
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| 280 | REG_RAD1_BAND_SELECT = (short)reg5; |
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| 281 | REG_RAD1_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 282 | REG_RAD1_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 283 | } |
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| 284 | if((radios & RAD2MASK) > 0) { |
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| 285 | |
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| 286 | reg5 = REG_RAD2_BAND_SELECT | mask5gl1; |
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| 287 | reg5 = reg5 & mask5gl2; |
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| 288 | |
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| 289 | transRadio(0x0002, ((reg5<<4)+0x0005)); |
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| 290 | transRadio(0x0002, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 291 | transRadio(0x0002, ((reg5<<4)+0x0005)); |
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| 292 | |
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| 293 | REG_RAD2_BAND_SELECT = (short)reg5; |
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| 294 | REG_RAD2_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 295 | REG_RAD2_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 296 | } |
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| 297 | if((radios & RAD3MASK) > 0) { |
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| 298 | |
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| 299 | reg5 = REG_RAD3_BAND_SELECT | mask5gl1; |
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| 300 | reg5 = reg5 & mask5gl2; |
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| 301 | |
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| 302 | transRadio(0x0004, ((reg5<<4)+0x0005)); |
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| 303 | transRadio(0x0004, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 304 | transRadio(0x0004, ((reg5<<4)+0x0005)); |
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| 305 | |
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| 306 | REG_RAD3_BAND_SELECT = (short)reg5; |
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| 307 | REG_RAD3_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 308 | REG_RAD3_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 309 | } |
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| 310 | if((radios & RAD4MASK) > 0) { |
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| 311 | |
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| 312 | reg5 = REG_RAD4_BAND_SELECT | mask5gl1; |
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| 313 | reg5 = reg5 & mask5gl2; |
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| 314 | |
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| 315 | transRadio(0x0008, ((reg5<<4)+0x0005)); |
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| 316 | transRadio(0x0008, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 317 | transRadio(0x0008, ((reg5<<4)+0x0005)); |
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| 318 | |
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| 319 | REG_RAD4_BAND_SELECT = (short)reg5; |
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| 320 | REG_RAD4_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 321 | REG_RAD4_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 322 | } |
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| 323 | } |
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| 324 | |
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| 325 | if (band5 == 2) { |
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| 326 | if((radios & RAD1MASK) > 0) { |
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| 327 | |
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| 328 | reg5 = REG_RAD1_BAND_SELECT | mask5gh; |
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| 329 | |
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| 330 | transRadio(0x0001, ((reg5<<4)+0x0005)); |
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| 331 | transRadio(0x0001, (((reg5 | 0x0080)<<4)+0x0002)); |
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| 332 | transRadio(0x0001, ((reg5<<4)+0x0005)); |
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| 333 | |
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| 334 | REG_RAD1_BAND_SELECT = (short)reg5; |
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| 335 | REG_RAD1_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 336 | REG_RAD1_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 337 | } |
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| 338 | if((radios & RAD2MASK) > 0) { |
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| 339 | |
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| 340 | reg5 = REG_RAD2_BAND_SELECT | mask5gh; |
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| 341 | |
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| 342 | transRadio(0x0002, ((reg5<<4)+0x0005)); |
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| 343 | transRadio(0x0002, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 344 | transRadio(0x0002, ((reg5<<4)+0x0005)); |
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| 345 | |
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| 346 | REG_RAD2_BAND_SELECT = (short)reg5; |
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| 347 | REG_RAD2_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 348 | REG_RAD2_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 349 | } |
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| 350 | if((radios & RAD3MASK) > 0) { |
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| 351 | |
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| 352 | reg5 = REG_RAD3_BAND_SELECT | mask5gh; |
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| 353 | |
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| 354 | transRadio(0x0004, ((reg5<<4)+0x0005)); |
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| 355 | transRadio(0x0004, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 356 | transRadio(0x0004, ((reg5<<4)+0x0005)); |
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| 357 | |
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| 358 | REG_RAD3_BAND_SELECT = (short)reg5; |
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| 359 | REG_RAD3_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 360 | REG_RAD3_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 361 | } |
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| 362 | if((radios & RAD4MASK) > 0) { |
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| 363 | |
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| 364 | reg5 = REG_RAD4_BAND_SELECT | mask5gh; |
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| 365 | |
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| 366 | transRadio(0x0008, ((reg5<<4)+0x0005)); |
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| 367 | transRadio(0x0008, (((reg5 | 0x0080)<<4)+0x0005)); |
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| 368 | transRadio(0x0008, ((reg5<<4)+0x0005)); |
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| 369 | |
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| 370 | REG_RAD4_BAND_SELECT = (short)reg5; |
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| 371 | REG_RAD4_INTEGER_DIVIDER_RATIO = (short)reg3; |
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| 372 | REG_RAD4_FRACTIONAL_DIVIDER_RATIO = (short)reg4; |
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| 373 | } |
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| 374 | } |
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| 375 | } |
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| 376 | |
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| 377 | |
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| 378 | RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) & ~(radios & RAD_24PA_MASK))); |
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| 379 | |
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| 380 | RADIO_CONTROLLER_mWriteSlaveReg1((volatile)radio_controller_baseaddr, (RADIO_CONTROLLER_mReadSlaveReg1((volatile)radio_controller_baseaddr) | (radios & RAD_5PA_MASK))); |
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| 381 | |
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| 382 | return retval; |
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| 383 | } |
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