root/ResearchApps/PHY/MIMO_OFDM/ofdm_rx_mimo_init.m

Revision 1024, 4.9 kB (checked in by murphpo, 22 hours ago)

Re-worked pilot phase calculation

Line 
1%Make sure the Tx init has already been loaded
2ofdm_tx_mimo_init;
3
4Symbol_Timing_Offset = 8; %15 = no offset
5PktDet_Delay = 26 + Symbol_Timing_Offset*2^7;
6
7
8pktByteNums =   numHeaderBytes + ...
9                                byteIndex_numPayloadBytes(1)*2^8 + ...
10                                byteIndex_numPayloadBytes(2)*2^16 + ...
11                                byteIndex_simpleDynModMasks * 2^24;
12
13rx_SISO_Mode = tx_SISO_Mode;
14
15%Load the packet timing control file
16ofdm_rx_init_packetTimingControl;
17
18%Packet detection threshold
19pkt_crossCorr_thresh = 0.7;
20pkt_energy_thresh = 0;
21
22
23%Interrupt control register has 8 bits:
24%0: Rx Pkt Interrupts Reset
25%1: Rx Header Interrupts Reset
26%2: Tx Done Interrupt Reset
27%3: Rx Good Pkt Interrupt Enable
28%4: Rx Bad Pkt Interrupt Enable
29%5: Rx Good Header Interrupt Enable
30%6: Rx Bad Header Interrupt Enable
31%7: Tx Done Interrupt Enable
32reg_InterruptControl = ...
33        0 + ...  %3 bits [RxPkt, RxHeader, TxDone] interrupt resets
34        15 * 2^3 + ... %4 bits[LSB:MSB]=[goodPkt, badPkt, goodHdr, badHdr] interrupt enables
35        0 * 2^7; %1 bit for TxDone enable
36
37%32-bit register holds both pkt buffer offsets (16LSB+8) and interrupt control (8LSB)
38reg_Interrupt_PktBuf_Control = ...
39        reg_InterruptControl + ...
40        1 * 2^16 + ... %6 bits for Tx pkt buff offset
41        0 * 2^24; %6 bits for Rx pkt buff offset
42       
43%Initialization values for the long correlator
44% The correlator only stores the signs of the values in a long trainin symbol
45% This code and the correlator block were designed by Dr. Chris Dick
46
47%Shift the correlation pattern by 16 to allow the calculation
48% to finish in time to decide the beginning of the payload
49%L = [longSymbol_time(50:64) longSymbol_time(1:49)];
50L = [longSymbol_time];
51
52ccr = -1*sign(real(fliplr(L)));
53ccr = [ccr 0];
54ii = find(ccr==0);
55ccr(ii)=1;
56
57cci = 1*sign(fliplr(imag(L)));
58cci = [cci 0];
59ii=find(cci==0);
60cci(ii)=1;
61
62ii = find(ccr==-1);
63hr = zeros(1,length(ccr));
64hr(ii) = 1;
65
66ii = find(cci==-1);
67hi = zeros(1,length(cci));
68hi(ii) = 1;
69
70long_cor_acc_n_bits = 4;
71Tr1 = 1/4;
72
73%Demodulator input precision
74symbol_unmap_bp= 15;
75symbol_unmap_nb= 16;
76
77
78%Popluate the RxControlBits register
79% Each bit has a different function
80%0x1:   1: Reset BER
81%0x2:   2: Require long correlation for pkt detection
82%0x4:   4: Enable dynamic packet lengths
83%0x8:   8: Big sub-pkt buffer mode (16KB max pkt size)
84%0x10:  16: Enable SISO mode
85%0x20:  32: Require 2 long correlations for pkt detection
86%0x40:  64: Require short correlation or ext pkt detection
87%0x80:  128: External pkt detection
88%0x100: 256: Internal Pkt Detection
89%0x200: 512: bypass CFO correction
90%0x400: 1024: Enable coarse CFO estimation
91%0x800: 2048: Use new coarse CFO calculation
92%0x1000:4096: Use LongCorr for CFO reset
93%0x2000:8192: Use real arctan for pilot phase calc
94%0x4000:16384: Bypass division during EQ
95
96%0x10000:65536: Enable simple dynamic modulation
97%0x20000:131072: Enable switching diversity
98%0x40000:262144: Use antenna B in SISO mode
99%0x80000:524288: Enable Rx reset on bad header CRC
100
101rx_controlBits = 1 * 2 ... %Long correlation
102                 + 1 * 4 ... %Dyn pkt lengths
103                 + 0 * 8 ... %1=big sub-pkt buffers
104                 + 1 * 16 * rx_SISO_Mode ...
105                 + 1 * 32 ... %2 long correlations
106                 + 1 * 64 ... %short correlation
107                 + 0 * 128 ... %ext pkt det
108                 + 1 * 256 ... %int pkt det
109                 + 0 * 512 ... %bypass CFO
110                 + 0 * 1024 ... %1=Enable coarse CFO estimation
111                 + 0 * 2048 ... %1=use new coarse CFO calc
112                 + 1 * 4096 ... %Long correlation for CFO
113                 + 1 * 8192 ... %Real arctan for CFO
114                 + 0 * 16384 ... %1=Bypass EQ division
115                 + 1 * 65536 ... %1=Use simple dynamic modulation
116                 + 1 * 131072 ... %1=Use switching diversity in SISO mode
117                 + 0 * 262144 ... %1=force AntB in SISO mode
118                 + 1 * 524288;    %1=Reset Rx on bad header
119
120%Post-equalization scaling
121%This value is used to scale the equalizer's output before demodulation
122%This is used to correct for any fixed gain/attenuation the full system has
123% The value shouldn't be channel or modulation dependent
124% It does depend on the number of training symbols (1/training)
125rxScaling = 2;
126
127% This scaling value resides in a UFix_32_0 register
128%  The value is split into two 16 bit values, then
129%   each is re-interpreted as a UFix_16_11
130rx_postEq_scaling = round(rxScaling*2^11) * (1 + 2^16);
131%mod((rxScaling*2^11),2^16) + (2^16 * mod((rxScaling*2^11),2^16));
132
133Rx_PhaseNoiseTrack_Kalpha = 0.5;
134Rx_PhaseNoiseTrack_Kbeta = 0.5;
135Rx_PhaseNoiseTrack_Kgamma = 0.5;
136
137Rx_PhaseNoiseTrack_K = 0.6094;%hex2dec('2700000')/2^26;
138%Rx_PhaseNoiseTrack_K = 0.15;
139
140freqOffset_track_filtCoef_p = hex2dec('d0000')/2^32;
141freqOffset_track_filtCoef_i = hex2dec('2500')/2^32;
142
143Rx_CoarseCFO_K = 0.2;
144
145%Load Chipscope capture data
146AntA_ADC_I = 0;AntA_ADC_Q = 0; csInterp = 1; t_start = 1;
147%xlloadchipScopeData('Y:\RxPkt_v00_QAM16_good.prn'); csInterp = 1; t_start = 350;
148
149rxAntI.time = [];
150rxAntQ.time = [];
151rxAntI.signals.values = AntA_ADC_I(t_start:csInterp:end);
152rxAntQ.signals.values = AntA_ADC_Q(t_start:csInterp:end);
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