[1818] | 1 | //////////////////////////////////////////////////////////////////////////////// |
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| 2 | // |
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[1869] | 3 | // File : warplab.c v6.3b |
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[1852] | 4 | // Date : 2012, November 16 |
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[1818] | 5 | // Author : P. Murphy, S. Gupta, M. Duarte, C. Hunter |
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| 6 | // |
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| 7 | // Changelog: |
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[1852] | 8 | // v6.3 |
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| 9 | // - No changes to C-code other than the print that says what version it is |
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| 10 | // - Small bugfixes to UCF for WARP v2 and WARP v3 |
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| 11 | // v6.2 |
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[1818] | 12 | // - This warplab.c is tailored to WARP v3. It will not compile on other hardware. |
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| 13 | // - Added support for WARPxilnet_v3_00 that adds support for the hard TEMACs |
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| 14 | // inside the Virtex4 |
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| 15 | // - v2 WARP hardware will use gigabit speeds by default. The Ethernet PHY |
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| 16 | // advertises its speed as gigabit, so there is no longer a need to |
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| 17 | // explicitly tell your computer to send at 100Mbit. |
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| 18 | // - Uses an XPS_Timer core to inact a timeout of WAITDURATION_SEC seconds |
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| 19 | // to wait for a sync packet. Previously, this timeout was handled by |
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| 20 | // waiting a set number of packets (e.g. 10 received packets). |
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| 21 | // - Moved the sync IP address up to a proper broadcast address of X.X.X.255. |
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| 22 | // This should obviate the need for explicit ARP table entries to handle |
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| 23 | // sync packets. The v06 WARPLAB M-Code Reference has correspondingly been |
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| 24 | // updated. |
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| 25 | // - This source file will compile for either v1 or v2 WARP hardware, assuming |
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| 26 | // the WARPxilnet and WARP_FPGA_BOARD software libraries are configured |
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| 27 | // |
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| 28 | //////////////////////////////////////////////////////////////////////////////// |
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| 29 | |
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| 30 | #include "xparameters.h" |
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| 31 | #include <xilnet_config.h> |
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| 32 | #include <xilnet_xilsock.h> |
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| 33 | #include <xilnet_mac.h> |
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| 34 | #include "xstatus.h" |
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| 35 | #include <stdlib.h> |
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| 36 | #include <string.h> |
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| 37 | #include "math.h" |
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| 38 | #include "radio_controller.h" |
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| 39 | #include "warplab_defines.h" |
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| 40 | #include "warplab_regmacros.h" |
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| 41 | #include "stdio.h" |
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| 42 | #include "xtmrctr.h" |
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| 43 | #include "w3_userio.h" |
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| 44 | #include "w3_ad_controller.h" |
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| 45 | #include "w3_clock_controller.h" |
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| 46 | #include "w3_iic_eeprom.h" |
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| 47 | #include "Xio.h" |
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| 48 | #include "xlltemac.h" |
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| 49 | #include "xllfifo.h" |
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| 50 | #include "xdmacentral.h" |
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| 51 | #include "xdmacentral_l.h" |
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| 52 | #include "warp_hw_ver.h" |
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| 53 | |
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| 54 | #define WARPLAB_MAJOR_VER 6 |
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[1852] | 55 | #define WARPLAB_MINOR_VER 3 |
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[1818] | 56 | |
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| 57 | #define RC_BASEADDR XPAR_RADIO_CONTROLLER_0_BASEADDR |
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| 58 | #define AD_BASEADDR XPAR_W3_AD_CONTROLLER_0_BASEADDR |
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| 59 | #define CLK_BASEADDR XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR |
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| 60 | #define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_0_BASEADDR |
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| 61 | #define USERIO_BASEADDR XPAR_W3_USERIO_0_BASEADDR |
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| 62 | #define TIMER_FREQ XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ |
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| 63 | #define WARPLAB_TXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO1 |
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| 64 | #define WARPLAB_TXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO2 |
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| 65 | #define WARPLAB_TXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO3 |
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| 66 | #define WARPLAB_TXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO4 |
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| 67 | #define WARPLAB_RXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO1 |
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| 68 | #define WARPLAB_RXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO2 |
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| 69 | #define WARPLAB_RXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO3 |
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| 70 | #define WARPLAB_RXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO4 |
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| 71 | #define WARPLAB_RSSIBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO1 |
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| 72 | #define WARPLAB_RSSIBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO2 |
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| 73 | #define WARPLAB_RSSIBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO3 |
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| 74 | #define WARPLAB_RSSIBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO4 |
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| 75 | #define TEMAC_DEVICE_ID XPAR_LLTEMAC_0_DEVICE_ID |
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| 76 | #define FIFO_DEVICE_ID XPAR_LLFIFO_0_DEVICE_ID |
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| 77 | #define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID |
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| 78 | #define TIMER_COUNTER_0 0 |
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| 79 | |
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| 80 | |
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| 81 | #define WARPLAB_CONFIG_2RF 1 // Comment in if board in 2x2 configuration |
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| 82 | //#define WARPLAB_CONFIG_4RF 1 // Comment in if board in 4x4 configuration |
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| 83 | // Currently not applicable to WARP v3 |
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| 84 | |
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| 85 | static XDmaCentral DmaCentralInst; |
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| 86 | static XDmaCentral_Config *DMAConfigPtr; |
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| 87 | XLlTemac TemacInstance; |
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| 88 | XLlTemac_Config *MacCfgPtr; |
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| 89 | XLlFifo FifoInstance; |
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| 90 | XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */ |
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| 91 | |
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| 92 | u8 numSync; |
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| 93 | u8 hw_generation; |
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| 94 | u8 numRadios; |
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| 95 | |
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| 96 | #define ENET_LINK_SPEED 1000 |
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| 97 | #define BUFSIZE 2000 |
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| 98 | #define DEBUG_LVL 0 |
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| 99 | |
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| 100 | |
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| 101 | #define WAITDURATION_SEC 2 |
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| 102 | |
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| 103 | unsigned int sendPtr32[(BUFSIZE+3)/4]; |
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| 104 | unsigned char * const sendBuffer = (unsigned char *) sendPtr32; |
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| 105 | unsigned int receivePtr32[(BUFSIZE+3)/4]; |
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| 106 | unsigned char * const receiveBuffer = (unsigned char *) receivePtr32; |
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| 107 | unsigned int myPort; |
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| 108 | |
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| 109 | int sock; // UDP socket |
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| 110 | struct sockaddr_in addr; |
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| 111 | unsigned int alen = 0; |
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| 112 | char node; |
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| 113 | |
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| 114 | unsigned int ReadWrite; |
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| 115 | unsigned char Radios_WirelessChan; |
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| 116 | unsigned char Radios_Tx_LPF_Corn_Freq; |
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| 117 | unsigned char Radios_Rx_LPF_Corn_Freq; |
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| 118 | unsigned char Radio1_TxGain_BB, Radio1_TxGain_RF, Radio1_RxGain_BB, Radio1_RxGain_RF; |
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| 119 | unsigned char Radio2_TxGain_BB, Radio2_TxGain_RF, Radio2_RxGain_BB, Radio2_RxGain_RF; |
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| 120 | unsigned char Radio3_TxGain_BB, Radio3_TxGain_RF, Radio3_RxGain_BB, Radio3_RxGain_RF; |
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| 121 | unsigned char Radio4_TxGain_BB, Radio4_TxGain_RF, Radio4_RxGain_BB, Radio4_RxGain_RF; |
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| 122 | |
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| 123 | unsigned int AgcIsDoneAddr; |
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| 124 | unsigned int MGC_AGC_Sel_Variable = 0; // By default MGC is selected |
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| 125 | |
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| 126 | //---------------------------------- |
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| 127 | // Functions |
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| 128 | void sendACK(unsigned int packetNo, unsigned int commandToACK); |
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| 129 | unsigned char sevenSegmentMap(unsigned char x); |
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| 130 | int warpphy_applyTxDCOCorrection(unsigned int radioSelection); |
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| 131 | void warplab_AGC_Reset(); |
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| 132 | void warplab_AGC_MasterReset(); |
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| 133 | void warplab_AGC_Start(); |
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| 134 | void warplab_AGC_Initialize(int noise_estimate); |
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| 135 | void warplab_AGC_setNoiseEstimate(int noise_estimate); |
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| 136 | unsigned int warplab_AGC_GetGains(void); |
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| 137 | void warplab_AGC_SetTarget(unsigned int target); |
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| 138 | void warplab_AGC_SetDCO(unsigned int AGCstate); |
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| 139 | int warpphy_applyTxDCOCalibration(unsigned int radioSelection); |
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| 140 | // In WARPLab there is no decimation filter in the AGC, there is a downsampling only, so in WARPLab a function equivalent to |
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| 141 | // ofdm_AGC_FiltSel is not needed |
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| 142 | |
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| 143 | int w3_node_init() { |
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| 144 | |
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| 145 | int status; |
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| 146 | XTmrCtr *TmrCtrInstancePtr = &TimerCounter; |
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| 147 | int ret = XST_SUCCESS; |
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| 148 | |
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| 149 | microblaze_enable_exceptions(); |
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| 150 | |
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| 151 | //Initialize the AD9512 clock buffers (RF reference and sampling clocks) |
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| 152 | status = clk_init(CLK_BASEADDR, 2); |
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| 153 | if(status != XST_SUCCESS) { |
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| 154 | xil_printf("w3_node_init: Error in clk_init (%d)\n", status); |
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| 155 | ret = XST_FAILURE; |
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| 156 | } |
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| 157 | //Update the sampling clock buffer config to divide the AD clocks by 2 for 40MHz sampling |
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| 158 | clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4B, 0x00); //OUT0 divider on |
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| 159 | clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4A, 0x00); //OUT0 divide by 2 |
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| 160 | clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4F, 0x00); //OUT2 divider on |
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| 161 | clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4E, 0x00); //OUT2 divide by 2 |
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| 162 | clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x5A, 0x01); //Self-clearing register update flag |
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| 163 | |
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| 164 | //Initialize the AD9963 ADCs/DACs |
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| 165 | status = ad_init(AD_BASEADDR, 2); |
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| 166 | if(status != XST_SUCCESS) { |
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| 167 | xil_printf("w3_node_init: Error in ad_init (%d)\n", status); |
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| 168 | ret = XST_FAILURE; |
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| 169 | } |
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| 170 | |
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| 171 | //Initialize the radio_controller core and MAX2829 transceivers |
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| 172 | status = radio_controller_init(RC_BASEADDR, (RC_RFA | RC_RFB), 1, 1); |
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| 173 | if(status != XST_SUCCESS) { |
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| 174 | xil_printf("w3_node_init: Error in radio_controller_initialize (%d)\n", status); |
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| 175 | ret = XST_FAILURE; |
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| 176 | } |
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| 177 | |
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| 178 | //Initialize the EEPROM read/write core |
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| 179 | iic_eeprom_init(EEPROM_BASEADDR, 0x64); |
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| 180 | if(status != XST_SUCCESS) { |
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| 181 | xil_printf("w3_node_init: Error in IIC_EEPROM_init (%d)\n", status); |
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| 182 | ret = XST_FAILURE; |
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| 183 | } |
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| 184 | |
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| 185 | /* |
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| 186 | * Initialize the timer counter so that it's ready to use, |
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| 187 | * specify the device ID that is generated in xparameters.h |
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| 188 | */ |
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| 189 | status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID); |
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| 190 | if (status != XST_SUCCESS) { |
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| 191 | xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status); |
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| 192 | ret = XST_FAILURE; |
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| 193 | } |
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| 194 | |
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| 195 | /* |
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| 196 | * Perform a self-test to ensure that the hardware was built |
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| 197 | * correctly, use the 1st timer in the device (0) |
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| 198 | */ |
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| 199 | status = XTmrCtr_SelfTest(TmrCtrInstancePtr, 0); |
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| 200 | if (status != XST_SUCCESS) { |
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| 201 | ret = XST_FAILURE; |
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| 202 | } |
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| 203 | |
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| 204 | // Set timer 0 to into a "count down" mode |
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| 205 | XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION)); |
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| 206 | |
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| 207 | ///// Project-Specific Initializations ///// |
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| 208 | node = userio_read_inputs(USERIO_BASEADDR)&W3_USERIO_DIPSW; |
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| 209 | userio_write_hexdisp_left(USERIO_BASEADDR, (node+1)%10); |
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| 210 | |
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| 211 | radio_controller_setTxGainSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_GAINSRC_SPI); |
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| 212 | radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_GAINSRC_SPI); |
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| 213 | |
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| 214 | radio_controller_apply_TxDCO_calibration(AD_BASEADDR, EEPROM_BASEADDR, (RC_RFA | RC_RFB)); |
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| 215 | |
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| 216 | //Set Tx bandwidth to nominal mode |
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| 217 | Radios_Tx_LPF_Corn_Freq = 1; |
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| 218 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA | RC_RFB), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq); |
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| 219 | |
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| 220 | //Set Rx bandwidth to nominal mode |
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| 221 | Radios_Rx_LPF_Corn_Freq = 1; |
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| 222 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA | RC_RFB), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq); |
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| 223 | |
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| 224 | //Set Radios to use 30KHz cutoff on HPF |
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| 225 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA | RC_RFB), RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 1); |
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| 226 | |
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| 227 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA | RC_RFB), RC_PARAMID_TXLINEARITY_VGA, 2); |
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| 228 | |
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| 229 | |
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| 230 | |
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| 231 | ///Timer Setup/// |
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| 232 | XTmrCtr_SetResetValue(TmrCtrInstancePtr,1,0); //Sets it so issuing a "start" command begins at counter=0 |
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| 233 | ///////////////// |
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| 234 | |
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| 235 | radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA | RC_RFB)); |
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| 236 | |
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| 237 | |
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| 238 | #ifdef WARP_HW_VER_v3 |
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| 239 | hw_generation = 3; |
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| 240 | #elif defined WARP_HW_VER_v2 |
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| 241 | hw_generation = 2; |
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| 242 | #elif defined WARP_HW_VER_v1 |
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| 243 | hw_generation = 1; |
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| 244 | #endif |
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| 245 | |
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| 246 | #ifdef WARPLAB_CONFIG_2RF |
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| 247 | numRadios = 2; |
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| 248 | #elif defined WARPLAB_CONFIG_4RF |
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| 249 | numRadios = 4; |
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| 250 | #endif |
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| 251 | |
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| 252 | |
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| 253 | |
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| 254 | return ret; |
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| 255 | } |
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| 256 | |
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| 257 | void usleep(u32 duration){ |
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| 258 | XTmrCtr *TmrCtrInstancePtr = &TimerCounter; |
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| 259 | XTmrCtr_SetResetValue(TmrCtrInstancePtr,0,duration*(TIMER_FREQ/1000000)); |
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| 260 | |
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| 261 | XTmrCtr_Start(TmrCtrInstancePtr,0); |
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| 262 | |
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| 263 | volatile u8 isExpired = 0; |
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| 264 | while(isExpired!=1){ |
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| 265 | isExpired = XTmrCtr_IsExpired(TmrCtrInstancePtr,0); |
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| 266 | } |
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| 267 | XTmrCtr_Reset(TmrCtrInstancePtr,0); |
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| 268 | return; |
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| 269 | } |
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| 270 | |
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| 271 | |
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| 272 | void init_net() { |
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| 273 | int Status; |
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| 274 | xil_printf("Configuring network\n"); |
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| 275 | |
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| 276 | mb_hw_addr[0] = 0x00; |
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| 277 | mb_hw_addr[1] = 0x50; |
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| 278 | mb_hw_addr[2] = 0xc2; |
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| 279 | mb_hw_addr[3] = 0x63; |
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| 280 | mb_hw_addr[4] = 0x36; |
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| 281 | mb_hw_addr[5] = node+0x63; |
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| 282 | |
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| 283 | mb_ip_addr[0] = 10; |
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| 284 | mb_ip_addr[1] = 0; |
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| 285 | mb_ip_addr[2] = 0; |
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| 286 | mb_ip_addr[3] = node+1; |
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| 287 | |
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| 288 | //Define the last octet of the IP address used for SYNC packets. The first three will be the mb_ip_addr. |
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| 289 | sync_IP_octet = 255; |
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| 290 | |
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| 291 | myPort = 9000 + node; |
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| 292 | |
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| 293 | xilnet_eth_init_hw_addr_tbl(); |
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| 294 | |
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| 295 | if(DEBUG_LVL > 1) xil_printf("... initializing DMA\n"); |
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| 296 | /**************************DMA*******************************/ |
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| 297 | //Lookup the DMA configuration information |
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| 298 | DMAConfigPtr = XDmaCentral_LookupConfig(XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID); |
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| 299 | |
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| 300 | //Initialize the config struct |
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| 301 | Status = XDmaCentral_CfgInitialize(&DmaCentralInst, DMAConfigPtr, DMAConfigPtr->BaseAddress); |
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| 302 | if (Status != XST_SUCCESS){ |
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| 303 | xil_printf("... ... DMA CfgInitialize failed!\n"); |
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| 304 | return; |
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| 305 | } |
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| 306 | |
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| 307 | //Disable Interrupts |
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| 308 | XDmaCentral_InterruptEnableSet(&DmaCentralInst, 0); |
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| 309 | if(DEBUG_LVL > 1) xil_printf("... ... complete!\n"); |
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| 310 | /************************************************************/ |
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| 311 | |
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| 312 | /*******************Ethernet**********************************/ |
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| 313 | if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet\n"); |
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| 314 | MacCfgPtr = XLlTemac_LookupConfig(TEMAC_DEVICE_ID); |
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| 315 | Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr, MacCfgPtr->BaseAddress); |
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| 316 | XLlFifo_Initialize(&FifoInstance, XLlTemac_LlDevBaseAddress(&TemacInstance)); |
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| 317 | if (Status != XST_SUCCESS) |
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| 318 | xil_printf("... ... EMAC init error\n"); |
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| 319 | |
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| 320 | if (!XLlTemac_IsFifo(&TemacInstance)) |
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| 321 | xil_printf("... ... EMAC hw config incorrect\n"); |
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| 322 | |
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| 323 | |
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| 324 | |
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| 325 | Status = XLlTemac_ClearOptions(&TemacInstance, XTE_LENTYPE_ERR_OPTION | XTE_FLOW_CONTROL_OPTION | XTE_FCS_STRIP_OPTION);// | XTE_MULTICAST_OPTION); |
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| 326 | Status |= XLlTemac_SetOptions(&TemacInstance, XTE_PROMISC_OPTION | XTE_MULTICAST_OPTION | XTE_BROADCAST_OPTION | XTE_RECEIVER_ENABLE_OPTION | XTE_TRANSMITTER_ENABLE_OPTION); //| XTE_JUMBO_OPTION |
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| 327 | if (Status != XST_SUCCESS) |
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| 328 | xil_printf("... ... Error setting EMAC options\n, code %d", Status); |
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| 329 | |
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| 330 | // Make sure the TEMAC is ready |
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| 331 | Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET); |
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| 332 | while ((Status & XTE_RDY_HARD_ACS_RDY_MASK) == 0) |
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| 333 | { |
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| 334 | Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET); |
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| 335 | } |
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| 336 | |
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| 337 | XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED); |
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| 338 | usleep(1 * 10000); |
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| 339 | |
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| 340 | XLlTemac_Start(&TemacInstance); |
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| 341 | if(DEBUG_LVL > 1) xil_printf("... ... complete!\n"); |
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| 342 | /************************************************************/ |
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| 343 | |
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| 344 | // Initialize the MAC OPB base address (MAC driver in net/mac.c) |
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| 345 | xilnet_mac_init((void *)&FifoInstance,(void *)&DmaCentralInst); |
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| 346 | |
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| 347 | |
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| 348 | if(DEBUG_LVL > 1) xil_printf("... complete!\n"); |
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| 349 | // Print IP address |
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| 350 | if(DEBUG_LVL > 0) xil_printf("IP Address: %d.%d.%d.%d \n", mb_ip_addr[0], mb_ip_addr[1],mb_ip_addr[2],mb_ip_addr[3]); |
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| 351 | } |
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| 352 | |
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| 353 | |
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| 354 | void init_socket() { |
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| 355 | |
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| 356 | sock = xilsock_socket(AF_INET, SOCK_DGRAM, 0); // Create UDP socket with domain Internet and UDP connection. |
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| 357 | if (sock == -1) { |
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| 358 | if(DEBUG_LVL > 0) xil_printf("Error in creating socket\n"); |
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| 359 | exit(-1); |
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| 360 | } |
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| 361 | |
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| 362 | addr.sin_family = AF_INET; |
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| 363 | addr.sin_port = myPort; |
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| 364 | addr.sin_addr.s_addr = INADDR_ANY; // Create the input socket with any incoming address. (0x00000000) |
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| 365 | |
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| 366 | XStatus bind = xilsock_bind(sock, (struct sockaddr *)&addr, sizeof(struct sockaddr)); |
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| 367 | if (bind == -1) { |
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| 368 | if(DEBUG_LVL > 0) xil_printf("Unable to bind socket\n"); |
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| 369 | exit(-1); |
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| 370 | } |
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| 371 | alen = sizeof(struct sockaddr); |
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| 372 | if(DEBUG_LVL > 0) xil_printf("Listening on UDP port %d.\n", myPort); |
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| 373 | } |
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| 374 | |
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| 375 | void shut_socket() { |
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| 376 | xilsock_close(sock); |
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| 377 | } |
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| 378 | |
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| 379 | int waitForSync() |
---|
| 380 | { |
---|
| 381 | unsigned int n; |
---|
| 382 | XTmrCtr *TmrCtrInstancePtr = &TimerCounter; |
---|
| 383 | XTmrCtr_Start(TmrCtrInstancePtr, 1); |
---|
| 384 | |
---|
| 385 | while(XTmrCtr_GetValue(TmrCtrInstancePtr, 1) < (WAITDURATION_SEC*XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ)){ |
---|
| 386 | n = xilnet_eth_recv_frame(receiveBuffer, BUFSIZE); |
---|
| 387 | if(n==9999) |
---|
| 388 | { |
---|
| 389 | //xil_printf("Got Sync\n"); |
---|
| 390 | numSync++; |
---|
| 391 | return 0; |
---|
| 392 | } |
---|
| 393 | } |
---|
| 394 | |
---|
| 395 | XTmrCtr_Stop(TmrCtrInstancePtr, 1); |
---|
| 396 | |
---|
| 397 | int numblinks; |
---|
| 398 | for(numblinks=0;numblinks<10;numblinks++){ |
---|
| 399 | userio_write_leds_red(USERIO_BASEADDR,0xF); |
---|
| 400 | usleep(100000); |
---|
| 401 | userio_write_leds_red(USERIO_BASEADDR,0x0); |
---|
| 402 | usleep(100000); |
---|
| 403 | userio_write_leds_red(USERIO_BASEADDR,0xF); |
---|
| 404 | } |
---|
| 405 | userio_write_leds_red(USERIO_BASEADDR,0x0); |
---|
| 406 | userio_write_leds_green(USERIO_BASEADDR,0x0); |
---|
| 407 | |
---|
| 408 | xil_printf("NoSync\n"); |
---|
| 409 | return 1; |
---|
| 410 | } |
---|
| 411 | |
---|
| 412 | int main() { |
---|
| 413 | |
---|
| 414 | int bytesReceived; |
---|
| 415 | int bytesSend; |
---|
| 416 | int command; |
---|
| 417 | int packetNo; |
---|
| 418 | int status; |
---|
| 419 | unsigned int rxArg0; |
---|
| 420 | char done = 0; |
---|
| 421 | unsigned char sevenSeg1 = 0x1; |
---|
| 422 | int agctarget = -14; |
---|
| 423 | int agcnoiseEst = -95; |
---|
| 424 | unsigned int agc_dco_state; |
---|
| 425 | |
---|
| 426 | status = w3_node_init(); |
---|
| 427 | if(status != 0) { |
---|
| 428 | xil_printf("Error in w3_node_init()! Exiting\n"); |
---|
| 429 | return -1; |
---|
| 430 | } |
---|
| 431 | |
---|
| 432 | //Initialize the xilnet stack & default sockets |
---|
| 433 | init_net(); |
---|
| 434 | init_socket(); |
---|
| 435 | |
---|
| 436 | #ifdef WARPLAB_CONFIG_2RF |
---|
[1869] | 437 | xil_printf("WARPLab v6.3b 2x2 Started - Waiting for connection from MATLAB\n"); |
---|
[1818] | 438 | #elif defined WARPLAB_CONFIG_4RF |
---|
[1869] | 439 | xil_printf("WARPLab v6.3b 4x4 Started - Waiting for connection from MATLAB\n"); |
---|
[1818] | 440 | #endif |
---|
| 441 | |
---|
| 442 | |
---|
| 443 | userio_write_leds_red(USERIO_BASEADDR,0x5); |
---|
| 444 | int numblinks; |
---|
| 445 | for(numblinks=0;numblinks<10;numblinks++){ |
---|
| 446 | userio_toggle_leds_red(USERIO_BASEADDR,0xF); |
---|
| 447 | usleep(100000); |
---|
| 448 | } |
---|
| 449 | userio_write_leds_red(USERIO_BASEADDR,0x0); |
---|
| 450 | userio_write_leds_green(USERIO_BASEADDR,0x0); |
---|
| 451 | |
---|
| 452 | XLlFifo_Reset(&FifoInstance); |
---|
| 453 | |
---|
| 454 | |
---|
| 455 | |
---|
| 456 | while(done == 0) { |
---|
| 457 | |
---|
| 458 | if(DEBUG_LVL > 3) xil_printf("|"); |
---|
| 459 | |
---|
| 460 | bytesReceived = xilsock_recvfrom(sock, receiveBuffer, BUFSIZE, (struct sockaddr *)&addr, &alen); // Wait to receive data |
---|
| 461 | |
---|
| 462 | if (bytesReceived > 0) { // Check for valid packet |
---|
| 463 | |
---|
| 464 | packetNo = receivePtr32[0]; |
---|
| 465 | command = receivePtr32[1]; |
---|
| 466 | rxArg0 = receivePtr32[2]; |
---|
| 467 | |
---|
| 468 | //Rotate the single active bit |
---|
| 469 | sevenSeg1 = ( ((sevenSeg1<<1)&0x7E) | ((sevenSeg1>>5)&0x7E) ); |
---|
| 470 | |
---|
| 471 | userio_write_hexdisp_right(USERIO_BASEADDR, sevenSeg1<<1); |
---|
| 472 | |
---|
| 473 | if(DEBUG_LVL > 2) xil_printf("=============\nPacket Received\n Length: %d\n Packet No.: %d\n Command No: %d\n", bytesReceived, packetNo, command); |
---|
| 474 | |
---|
| 475 | switch(command) { // Decode on incoming command |
---|
| 476 | |
---|
| 477 | case INITIALIZE: |
---|
| 478 | //if(DEBUG_LVL > 1) xil_printf("Initializing Node..."); |
---|
| 479 | warplab_buffers_WriteReg_TxDelay(0); |
---|
| 480 | warplab_buffers_WriteReg_StartCapture(0); |
---|
| 481 | warplab_buffers_WriteReg_TxLength((unsigned int)16383); |
---|
| 482 | warplab_buffers_WriteReg_TransMode(0); |
---|
| 483 | warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0); |
---|
| 484 | warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0); |
---|
| 485 | warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0); |
---|
| 486 | warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0); |
---|
| 487 | warplab_AGC_WriteReg_RADIO1_AGC_EN(0); // No radio on slot 1 |
---|
| 488 | warplab_AGC_WriteReg_RADIO2_AGC_EN(0); |
---|
| 489 | warplab_AGC_WriteReg_RADIO3_AGC_EN(0); |
---|
| 490 | warplab_AGC_WriteReg_RADIO4_AGC_EN(0); // No radio on slot 4 |
---|
| 491 | warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)50); |
---|
| 492 | warplab_buffers_WriteReg_MGC_AGC_SEL(0);// Select MGC by default |
---|
| 493 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
| 494 | MGC_AGC_Sel_Variable = 0; |
---|
| 495 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 496 | warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0); |
---|
| 497 | warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0); |
---|
| 498 | warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0); |
---|
| 499 | warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0); |
---|
| 500 | #endif |
---|
| 501 | sendACK(packetNo, command); |
---|
| 502 | break; |
---|
| 503 | |
---|
| 504 | case NETWORKCHECK: |
---|
| 505 | sendPtr32[0] = packetNo + 1; |
---|
| 506 | sendPtr32[1] = ACK; |
---|
| 507 | sendPtr32[2] = command; |
---|
| 508 | sendPtr32[3] = numSync; |
---|
| 509 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 510 | numSync = 0; |
---|
| 511 | waitForSync(); |
---|
| 512 | break; |
---|
| 513 | |
---|
| 514 | case BOARDINFO: |
---|
| 515 | sendPtr32[0] = packetNo + 1; |
---|
| 516 | sendPtr32[1] = ACK; |
---|
| 517 | sendPtr32[2] = command; |
---|
| 518 | sendPtr32[3] = w3_eeprom_readSerialNum(EEPROM_BASEADDR); |
---|
| 519 | sendPtr32[4] = userio_read_fpga_dna_msb(USERIO_BASEADDR); |
---|
| 520 | sendPtr32[5] = userio_read_fpga_dna_lsb(USERIO_BASEADDR); |
---|
| 521 | sendPtr32[6] = (hw_generation<<24)|(numRadios<<16)|(WARPLAB_MAJOR_VER<<8)|(WARPLAB_MINOR_VER); |
---|
| 522 | xilsock_sendto(sock, sendBuffer, 28, (struct sockaddr *)&addr, alen); |
---|
| 523 | break; |
---|
| 524 | |
---|
| 525 | case TX_DELAY: |
---|
| 526 | |
---|
| 527 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
| 528 | if(0 == ReadWrite) |
---|
| 529 | { |
---|
| 530 | sendPtr32[0] = packetNo + 1; |
---|
| 531 | sendPtr32[1] = ACK; |
---|
| 532 | sendPtr32[2] = command; |
---|
| 533 | |
---|
| 534 | sendPtr32[3] = warplab_mimo_ReadReg_TxDelay(WARPLAB_BASEADDR); |
---|
| 535 | |
---|
| 536 | if(DEBUG_LVL > 2) xil_printf("Read capt offset of %d\n", (unsigned int)receivePtr32[3]); |
---|
| 537 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 538 | } |
---|
| 539 | if(1 == ReadWrite) |
---|
| 540 | { |
---|
| 541 | //If the user requests a TX_DELAY that's too big, write the maximum instead |
---|
| 542 | warplab_buffers_WriteReg_TxDelay((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]); |
---|
| 543 | if(DEBUG_LVL > 2) xil_printf("Set capt offset to %d\n", (unsigned int)receivePtr32[3]); |
---|
| 544 | sendACK(packetNo, command); |
---|
| 545 | } |
---|
| 546 | |
---|
| 547 | break; |
---|
| 548 | |
---|
| 549 | case TX_LENGTH: |
---|
| 550 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
| 551 | if(0 == ReadWrite) |
---|
| 552 | { |
---|
| 553 | sendPtr32[0] = packetNo + 1; |
---|
| 554 | sendPtr32[1] = ACK; |
---|
| 555 | sendPtr32[2] = command; |
---|
| 556 | |
---|
| 557 | sendPtr32[3] = warplab_mimo_ReadReg_TxLength(WARPLAB_BASEADDR); |
---|
| 558 | |
---|
| 559 | if(DEBUG_LVL > 2) xil_printf("Read TxLength of %d\n", (unsigned int)receivePtr32[3]); |
---|
| 560 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 561 | } |
---|
| 562 | if(1 == ReadWrite) |
---|
| 563 | { |
---|
| 564 | //If the user requests a TX_LENGTH that's too big, write the maximum instead |
---|
| 565 | warplab_buffers_WriteReg_TxLength((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]); |
---|
| 566 | if(DEBUG_LVL > 2) xil_printf("Set TxLength to %d\n", (unsigned int)receivePtr32[3]); |
---|
| 567 | sendACK(packetNo, command); |
---|
| 568 | } |
---|
| 569 | break; |
---|
| 570 | |
---|
| 571 | case TX_MODE: |
---|
| 572 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
| 573 | if(0 == ReadWrite) |
---|
| 574 | { |
---|
| 575 | sendPtr32[0] = packetNo + 1; |
---|
| 576 | sendPtr32[1] = ACK; |
---|
| 577 | sendPtr32[2] = command; |
---|
| 578 | |
---|
| 579 | sendPtr32[3] = warplab_mimo_ReadReg_TransMode(WARPLAB_BASEADDR); |
---|
| 580 | |
---|
| 581 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 582 | } |
---|
| 583 | if(1 == ReadWrite) |
---|
| 584 | { |
---|
| 585 | warplab_buffers_WriteReg_TransMode((unsigned int)receivePtr32[3]); |
---|
| 586 | sendACK(packetNo, command); |
---|
| 587 | } |
---|
| 588 | break; |
---|
| 589 | |
---|
| 590 | |
---|
| 591 | case RX1BUFFERS_DEBUG: |
---|
| 592 | |
---|
| 593 | break; |
---|
| 594 | |
---|
| 595 | case RX2BUFFERS_DEBUG: |
---|
| 596 | |
---|
| 597 | break; |
---|
| 598 | |
---|
| 599 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 600 | case RX3BUFFERS_DEBUG: |
---|
| 601 | |
---|
| 602 | break; |
---|
| 603 | |
---|
| 604 | case RX4BUFFERS_DEBUG: |
---|
| 605 | |
---|
| 606 | break; |
---|
| 607 | #endif |
---|
| 608 | |
---|
| 609 | case MGC_AGC_SEL: |
---|
| 610 | //ReadWrite = (unsigned int)receivePtr32[2]; |
---|
| 611 | MGC_AGC_Sel_Variable = (unsigned int)receivePtr32[2]; |
---|
| 612 | //if(0 == ReadWrite) |
---|
| 613 | //{ |
---|
| 614 | // sendPtr32[0] = packetNo + 1; |
---|
| 615 | // sendPtr32[1] = ACK; |
---|
| 616 | // sendPtr32[2] = command; |
---|
| 617 | |
---|
| 618 | // sendPtr32[3] = warplab_mimo_4x4_ReadReg_MGC_AGC_SEL(XPAR_WARPLAB_MIMO_4X4_OPBW_0_BASEADDR); |
---|
| 619 | |
---|
| 620 | // xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 621 | //} |
---|
| 622 | //if(1 == ReadWrite) |
---|
| 623 | //{ |
---|
| 624 | warplab_buffers_WriteReg_MGC_AGC_SEL(MGC_AGC_Sel_Variable); |
---|
| 625 | |
---|
| 626 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 627 | { |
---|
| 628 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
| 629 | radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG); |
---|
| 630 | radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_GAINSRC_SPI); |
---|
| 631 | } |
---|
| 632 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 633 | { |
---|
| 634 | radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_HW); |
---|
| 635 | radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_GAINSRC_HW); |
---|
| 636 | |
---|
| 637 | // Initialize the AGC |
---|
| 638 | warplab_AGC_Initialize(agcnoiseEst); |
---|
| 639 | warplab_AGC_setNoiseEstimate(agcnoiseEst); |
---|
| 640 | // ofdm_AGC_FiltSel(0); No decimation option in WARPLab AGC |
---|
| 641 | warplab_AGC_SetDCO(0); |
---|
| 642 | warplab_AGC_SetTarget(agctarget); |
---|
| 643 | warplab_AGC_Reset(); |
---|
| 644 | } |
---|
| 645 | |
---|
| 646 | sendACK(packetNo, command); |
---|
| 647 | //} |
---|
| 648 | break; |
---|
| 649 | |
---|
| 650 | case CARRIER_CHANNEL: |
---|
| 651 | Radios_WirelessChan = ((unsigned int)receivePtr32[2]); |
---|
| 652 | |
---|
| 653 | //Channels in [1...37] are valid |
---|
| 654 | // Values in [1...14] select 2.4GHz channels [1...14] |
---|
| 655 | // Values in [15...37] select a 5GHz channels [1...23] |
---|
| 656 | if(Radios_WirelessChan <= (14+23)) |
---|
| 657 | { |
---|
| 658 | if(Radios_WirelessChan <= 14) { |
---|
| 659 | radio_controller_setCenterFrequency(RC_BASEADDR, (RC_RFA|RC_RFB), RC_24GHZ, Radios_WirelessChan); |
---|
| 660 | } else { |
---|
| 661 | radio_controller_setCenterFrequency(RC_BASEADDR, (RC_RFA|RC_RFB), RC_5GHZ, (Radios_WirelessChan-14)); |
---|
| 662 | } |
---|
| 663 | } |
---|
| 664 | |
---|
| 665 | sendACK(packetNo, command); |
---|
| 666 | break; |
---|
| 667 | |
---|
| 668 | case TX_LPF_CORN_FREQ: |
---|
| 669 | Radios_Tx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]); |
---|
| 670 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA|RC_RFB), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq&0x3); |
---|
| 671 | sendACK(packetNo, command); |
---|
| 672 | break; |
---|
| 673 | |
---|
| 674 | case RX_LPF_CORN_FREQ: |
---|
| 675 | Radios_Rx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]); |
---|
| 676 | radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA|RC_RFB), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq&0x3); |
---|
| 677 | sendACK(packetNo, command); |
---|
| 678 | break; |
---|
| 679 | |
---|
| 680 | |
---|
| 681 | case RADIO1_TXGAINS: |
---|
| 682 | //Extract the radio gain config options from the received Ethernet packet |
---|
| 683 | Radio1_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
| 684 | Radio1_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
| 685 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_BB, Radio1_TxGain_BB); |
---|
| 686 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_RF, Radio1_TxGain_RF); |
---|
| 687 | //radio_controller_setTxGainTarget(RC_BASEADDR, RC_RFA, Radio1_TxGain_RF); |
---|
| 688 | sendACK(packetNo, command); |
---|
| 689 | break; |
---|
| 690 | |
---|
| 691 | case RADIO1_RXGAINS: |
---|
| 692 | //Extract the radio gain config options from the received Ethernet packet |
---|
| 693 | Radio1_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
| 694 | Radio1_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
| 695 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_BB, Radio1_RxGain_BB); |
---|
| 696 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_RF, Radio1_RxGain_RF); |
---|
| 697 | sendACK(packetNo, command); |
---|
| 698 | break; |
---|
| 699 | |
---|
| 700 | case RADIO2_TXGAINS: |
---|
| 701 | //Extract the radio gain config options from the received Ethernet packet |
---|
| 702 | Radio2_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
| 703 | Radio2_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
| 704 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_BB, Radio2_TxGain_BB); |
---|
| 705 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_RF, Radio2_TxGain_RF); |
---|
| 706 | sendACK(packetNo, command); |
---|
| 707 | break; |
---|
| 708 | |
---|
| 709 | case RADIO2_RXGAINS: |
---|
| 710 | //Extract the radio gain config options from the received Ethernet packet |
---|
| 711 | Radio2_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
| 712 | Radio2_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
| 713 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_BB, Radio2_RxGain_BB); |
---|
| 714 | radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_RF, Radio2_RxGain_RF); |
---|
| 715 | sendACK(packetNo, command); |
---|
| 716 | break; |
---|
| 717 | |
---|
| 718 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 719 | case RADIO3_TXGAINS: |
---|
| 720 | sendACK(packetNo, command); |
---|
| 721 | break; |
---|
| 722 | |
---|
| 723 | case RADIO3_RXGAINS: |
---|
| 724 | sendACK(packetNo, command); |
---|
| 725 | break; |
---|
| 726 | |
---|
| 727 | case RADIO4_TXGAINS: |
---|
| 728 | sendACK(packetNo, command); |
---|
| 729 | break; |
---|
| 730 | |
---|
| 731 | case RADIO4_RXGAINS: |
---|
| 732 | sendACK(packetNo, command); |
---|
| 733 | break; |
---|
| 734 | #endif |
---|
| 735 | |
---|
| 736 | |
---|
| 737 | case RADIO1_TXEN: |
---|
| 738 | radio_controller_TxEnable(RC_BASEADDR, (RC_RFA)); |
---|
| 739 | |
---|
| 740 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Enabled\n"); |
---|
| 741 | sendACK(packetNo, command); |
---|
| 742 | break; |
---|
| 743 | |
---|
| 744 | case RADIO2_TXEN: |
---|
| 745 | radio_controller_TxEnable(RC_BASEADDR, (RC_RFB)); |
---|
| 746 | |
---|
| 747 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Enabled\n"); |
---|
| 748 | sendACK(packetNo, command); |
---|
| 749 | break; |
---|
| 750 | |
---|
| 751 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 752 | case RADIO3_TXEN: |
---|
| 753 | sendACK(packetNo, command); |
---|
| 754 | break; |
---|
| 755 | |
---|
| 756 | |
---|
| 757 | case RADIO4_TXEN: |
---|
| 758 | sendACK(packetNo, command); |
---|
| 759 | break; |
---|
| 760 | #endif |
---|
| 761 | |
---|
| 762 | case RADIO1_TXDIS: |
---|
| 763 | radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA)); |
---|
| 764 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\n"); |
---|
| 765 | sendACK(packetNo, command); |
---|
| 766 | break; |
---|
| 767 | |
---|
| 768 | case RADIO2_TXDIS: |
---|
| 769 | radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB)); |
---|
| 770 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\n"); |
---|
| 771 | sendACK(packetNo, command); |
---|
| 772 | break; |
---|
| 773 | |
---|
| 774 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 775 | case RADIO3_TXDIS: |
---|
| 776 | sendACK(packetNo, command); |
---|
| 777 | break; |
---|
| 778 | |
---|
| 779 | case RADIO4_TXDIS: |
---|
| 780 | sendACK(packetNo, command); |
---|
| 781 | break; |
---|
| 782 | #endif |
---|
| 783 | |
---|
| 784 | case RADIO1_RXEN: |
---|
| 785 | /***************** Setup the radio board ************/ |
---|
| 786 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 787 | { |
---|
| 788 | // Disable the Rx HP filter |
---|
| 789 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 790 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 791 | // is controlled by the AGC core |
---|
| 792 | radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_OFF); |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | // usleep(10); |
---|
| 796 | |
---|
| 797 | //Enable the receiver |
---|
| 798 | radio_controller_RxEnable(RC_BASEADDR, (RC_RFA)); |
---|
| 799 | |
---|
| 800 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 801 | { |
---|
| 802 | //Enable this radio's AGC if user has set AGC Mode |
---|
| 803 | warplab_AGC_WriteReg_RADIO1_AGC_EN(1); |
---|
| 804 | } |
---|
| 805 | |
---|
| 806 | /***************** END Setup the radio board ************/ |
---|
| 807 | |
---|
| 808 | //if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n"); |
---|
| 809 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n"); |
---|
| 810 | sendACK(packetNo, command); |
---|
| 811 | break; |
---|
| 812 | |
---|
| 813 | case RADIO2_RXEN: |
---|
| 814 | |
---|
| 815 | /***************** Setup the radio board ************/ |
---|
| 816 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 817 | { |
---|
| 818 | // Disable the Rx HP filter |
---|
| 819 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 820 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 821 | // is controlled by the AGC core |
---|
| 822 | //WarpRadio_v1_RxHpDisable(radio2); |
---|
| 823 | radio_controller_setRxHP(RC_BASEADDR, (RC_RFB), RC_RXHP_OFF); |
---|
| 824 | } |
---|
| 825 | |
---|
| 826 | // usleep(10); |
---|
| 827 | |
---|
| 828 | //Enable the receiver |
---|
| 829 | radio_controller_RxEnable(RC_BASEADDR, (RC_RFB)); |
---|
| 830 | |
---|
| 831 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 832 | { |
---|
| 833 | //Enable this radio's AGC if user has set AGC Mode |
---|
| 834 | warplab_AGC_WriteReg_RADIO2_AGC_EN(1); |
---|
| 835 | } |
---|
| 836 | |
---|
| 837 | /***************** END Setup the radio board ************/ |
---|
| 838 | |
---|
| 839 | //if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n"); |
---|
| 840 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n"); |
---|
| 841 | sendACK(packetNo, command); |
---|
| 842 | break; |
---|
| 843 | |
---|
| 844 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 845 | case RADIO3_RXEN: |
---|
| 846 | sendACK(packetNo, command); |
---|
| 847 | break; |
---|
| 848 | |
---|
| 849 | case RADIO4_RXEN: |
---|
| 850 | sendACK(packetNo, command); |
---|
| 851 | break; |
---|
| 852 | #endif |
---|
| 853 | |
---|
| 854 | case RADIO1_RXDIS: |
---|
| 855 | radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA)); |
---|
| 856 | |
---|
| 857 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 858 | { |
---|
| 859 | //Enable the Rx HP filter |
---|
| 860 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 861 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 862 | // is controlled by the AGC core |
---|
| 863 | radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_ON); |
---|
| 864 | } |
---|
| 865 | |
---|
| 866 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 867 | { |
---|
| 868 | //Disable this radio's AGC if user has set AGC Mode |
---|
| 869 | warplab_AGC_WriteReg_RADIO1_AGC_EN(0); |
---|
| 870 | } |
---|
| 871 | |
---|
| 872 | //if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n"); |
---|
| 873 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n"); |
---|
| 874 | sendACK(packetNo, command); |
---|
| 875 | break; |
---|
| 876 | |
---|
| 877 | case RADIO2_RXDIS: |
---|
| 878 | radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB)); |
---|
| 879 | |
---|
| 880 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 881 | { |
---|
| 882 | //Enable the Rx HP filter |
---|
| 883 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 884 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 885 | // is controlled by the AGC core |
---|
[1869] | 886 | radio_controller_setRxHP(RC_BASEADDR, (RC_RFB), RC_RXHP_ON); |
---|
[1818] | 887 | } |
---|
| 888 | |
---|
| 889 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 890 | { |
---|
| 891 | //Disable this radio's AGC if user has set AGC Mode |
---|
| 892 | warplab_AGC_WriteReg_RADIO2_AGC_EN(0); |
---|
| 893 | } |
---|
| 894 | |
---|
| 895 | //if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n"); |
---|
| 896 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n"); |
---|
| 897 | sendACK(packetNo, command); |
---|
| 898 | break; |
---|
| 899 | |
---|
| 900 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 901 | case RADIO3_RXDIS: |
---|
| 902 | WarpRadio_v1_TxRxDisable(radio3); |
---|
| 903 | |
---|
| 904 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 905 | { |
---|
| 906 | //Enable the Rx HP filter |
---|
| 907 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 908 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 909 | // is controlled by the AGC core |
---|
| 910 | WarpRadio_v1_RxHpEnable(radio3); |
---|
| 911 | } |
---|
| 912 | |
---|
| 913 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 914 | { |
---|
| 915 | //Disable this radio's AGC if user has set AGC Mode |
---|
| 916 | warplab_AGC_WriteReg_RADIO3_AGC_EN(0); |
---|
| 917 | } |
---|
| 918 | |
---|
| 919 | //if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n"); |
---|
| 920 | if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n"); |
---|
| 921 | sendACK(packetNo, command); |
---|
| 922 | break; |
---|
| 923 | |
---|
| 924 | case RADIO4_RXDIS: |
---|
| 925 | WarpRadio_v1_TxRxDisable(radio4); |
---|
| 926 | |
---|
| 927 | if(0 == MGC_AGC_Sel_Variable) |
---|
| 928 | { |
---|
| 929 | //Enable the Rx HP filter |
---|
| 930 | // Only needed in Manual Gain Control (MGC) Mode |
---|
| 931 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
| 932 | // is controlled by the AGC core |
---|
| 933 | WarpRadio_v1_RxHpEnable(radio4); |
---|
| 934 | } |
---|
| 935 | |
---|
| 936 | if(1 == MGC_AGC_Sel_Variable) |
---|
| 937 | { |
---|
| 938 | //Disable this radio's AGC if user has set AGC Mode |
---|
| 939 | warplab_AGC_WriteReg_RADIO4_AGC_EN(0); |
---|
| 940 | } |
---|
| 941 | |
---|
| 942 | //if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n"); |
---|
| 943 | if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n"); |
---|
| 944 | sendACK(packetNo, command); |
---|
| 945 | break; |
---|
| 946 | #endif |
---|
| 947 | |
---|
| 948 | case RADIO1_TXDATA: |
---|
| 949 | memcpy |
---|
| 950 | ( |
---|
| 951 | (unsigned int *)(WARPLAB_TXBUFF_RADIO1 + 4*rxArg0),\ |
---|
| 952 | (unsigned int *)(receivePtr32 + 3),\ |
---|
| 953 | (bytesReceived-12) |
---|
| 954 | ); |
---|
| 955 | sendACK(packetNo, command); |
---|
| 956 | break; |
---|
| 957 | |
---|
| 958 | case RADIO2_TXDATA: |
---|
| 959 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0); |
---|
| 960 | //if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", *(unsigned int *)(receivePtr32 + 3), *(unsigned int *)(receivePtr32 + 4), *(unsigned int *)(receivePtr32 + 5), *(unsigned int *)(receivePtr32 + 6)); |
---|
| 961 | |
---|
| 962 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0); |
---|
| 963 | |
---|
| 964 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0); |
---|
| 965 | |
---|
| 966 | memcpy |
---|
| 967 | ( |
---|
| 968 | (unsigned int *)(WARPLAB_TXBUFF_RADIO2 + 4*rxArg0),\ |
---|
| 969 | (unsigned int *)(receivePtr32 + 3),\ |
---|
| 970 | (bytesReceived-12) |
---|
| 971 | ); |
---|
| 972 | |
---|
| 973 | sendACK(packetNo, command); |
---|
| 974 | break; |
---|
| 975 | |
---|
| 976 | |
---|
| 977 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 978 | case RADIO3_TXDATA: |
---|
| 979 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0); |
---|
| 980 | //if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", *(unsigned int *)(receivePtr32 + 3), *(unsigned int *)(receivePtr32 + 4), *(unsigned int *)(receivePtr32 + 5), *(unsigned int *)(receivePtr32 + 6)); |
---|
| 981 | |
---|
| 982 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0); |
---|
| 983 | |
---|
| 984 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0); |
---|
| 985 | /* |
---|
| 986 | memcpy |
---|
| 987 | ( |
---|
| 988 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
| 989 | (unsigned int *)(receivePtr32 + 3),\ |
---|
| 990 | (bytesReceived-12) |
---|
| 991 | ); |
---|
| 992 | */ |
---|
| 993 | memcpy |
---|
| 994 | ( |
---|
| 995 | (unsigned int *)(WARPLAB_TXBUFF_RADIO3 + 4*rxArg0),\ |
---|
| 996 | (unsigned int *)(receivePtr32 + 3),\ |
---|
| 997 | (bytesReceived-12) |
---|
| 998 | ); |
---|
| 999 | sendACK(packetNo, command); |
---|
| 1000 | break; |
---|
| 1001 | |
---|
| 1002 | case RADIO4_TXDATA: |
---|
| 1003 | memcpy |
---|
| 1004 | ( |
---|
| 1005 | (unsigned int *)(WARPLAB_TXBUFF_RADIO4 + 4*rxArg0),\ |
---|
| 1006 | (unsigned int *)(receivePtr32 + 3),\ |
---|
| 1007 | (bytesReceived-12) |
---|
| 1008 | ); |
---|
| 1009 | sendACK(packetNo, command); |
---|
| 1010 | break; |
---|
| 1011 | #endif |
---|
| 1012 | |
---|
| 1013 | |
---|
| 1014 | case RADIO1_RXDATA: |
---|
| 1015 | memcpy |
---|
| 1016 | ( |
---|
| 1017 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1018 | (unsigned int *)(WARPLAB_RXBUFF_RADIO1 + 4*rxArg0),\ |
---|
| 1019 | 1024 |
---|
| 1020 | ); |
---|
| 1021 | |
---|
| 1022 | sendPtr32[0] = packetNo + 1; |
---|
| 1023 | sendPtr32[1] = ACK; |
---|
| 1024 | sendPtr32[2] = command; |
---|
| 1025 | sendPtr32[3] = rxArg0; |
---|
| 1026 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1027 | break; |
---|
| 1028 | |
---|
| 1029 | case RADIO2_RXDATA: |
---|
| 1030 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
| 1031 | |
---|
| 1032 | /* |
---|
| 1033 | memcpy |
---|
| 1034 | ( |
---|
| 1035 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1036 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + 4*rxArg0),\ |
---|
| 1037 | 1024 |
---|
| 1038 | ); |
---|
| 1039 | */ |
---|
| 1040 | memcpy |
---|
| 1041 | ( |
---|
| 1042 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1043 | (unsigned int *)(WARPLAB_RXBUFF_RADIO2 + 4*rxArg0),\ |
---|
| 1044 | 1024 |
---|
| 1045 | ); |
---|
| 1046 | |
---|
| 1047 | //if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0); |
---|
| 1048 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + rxArg0)); |
---|
| 1049 | |
---|
| 1050 | sendPtr32[0] = packetNo + 1; |
---|
| 1051 | sendPtr32[1] = ACK; |
---|
| 1052 | sendPtr32[2] = command; |
---|
| 1053 | sendPtr32[3] = rxArg0; |
---|
| 1054 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1055 | break; |
---|
| 1056 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1057 | case RADIO3_RXDATA: |
---|
| 1058 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
| 1059 | |
---|
| 1060 | /* |
---|
| 1061 | memcpy |
---|
| 1062 | ( |
---|
| 1063 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1064 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
| 1065 | 1024 |
---|
| 1066 | ); |
---|
| 1067 | */ |
---|
| 1068 | memcpy |
---|
| 1069 | ( |
---|
| 1070 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1071 | (unsigned int *)(WARPLAB_RXBUFF_RADIO3 + 4*rxArg0),\ |
---|
| 1072 | 1024 |
---|
| 1073 | ); |
---|
| 1074 | |
---|
| 1075 | |
---|
| 1076 | //if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0); |
---|
| 1077 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + rxArg0)); |
---|
| 1078 | |
---|
| 1079 | sendPtr32[0] = packetNo + 1; |
---|
| 1080 | sendPtr32[1] = ACK; |
---|
| 1081 | sendPtr32[2] = command; |
---|
| 1082 | sendPtr32[3] = rxArg0; |
---|
| 1083 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1084 | break; |
---|
| 1085 | |
---|
| 1086 | case RADIO4_RXDATA: |
---|
| 1087 | memcpy |
---|
| 1088 | ( |
---|
| 1089 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1090 | (unsigned int *)(WARPLAB_RXBUFF_RADIO4 + 4*rxArg0),\ |
---|
| 1091 | 1024 |
---|
| 1092 | ); |
---|
| 1093 | |
---|
| 1094 | sendPtr32[0] = packetNo + 1; |
---|
| 1095 | sendPtr32[1] = ACK; |
---|
| 1096 | sendPtr32[2] = command; |
---|
| 1097 | sendPtr32[3] = rxArg0; |
---|
| 1098 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1099 | break; |
---|
| 1100 | #endif |
---|
| 1101 | |
---|
| 1102 | |
---|
| 1103 | case RADIO1_RSSIDATA: |
---|
| 1104 | memcpy |
---|
| 1105 | ( |
---|
| 1106 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1107 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO1 + 4*rxArg0),\ |
---|
| 1108 | 1024 |
---|
| 1109 | ); |
---|
| 1110 | sendPtr32[0] = packetNo + 1; |
---|
| 1111 | sendPtr32[1] = ACK; |
---|
| 1112 | sendPtr32[2] = command; |
---|
| 1113 | sendPtr32[3] = rxArg0; |
---|
| 1114 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1115 | break; |
---|
| 1116 | |
---|
| 1117 | case RADIO2_RSSIDATA: |
---|
| 1118 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
| 1119 | |
---|
| 1120 | /* |
---|
| 1121 | memcpy |
---|
| 1122 | ( |
---|
| 1123 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1124 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0),\ |
---|
| 1125 | 1024 |
---|
| 1126 | ); |
---|
| 1127 | */ |
---|
| 1128 | memcpy |
---|
| 1129 | ( |
---|
| 1130 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1131 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO2 + 4*rxArg0),\ |
---|
| 1132 | 1024 |
---|
| 1133 | ); |
---|
| 1134 | |
---|
| 1135 | |
---|
| 1136 | //if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0); |
---|
| 1137 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0)); |
---|
| 1138 | |
---|
| 1139 | sendPtr32[0] = packetNo + 1; |
---|
| 1140 | sendPtr32[1] = ACK; |
---|
| 1141 | sendPtr32[2] = command; |
---|
| 1142 | sendPtr32[3] = rxArg0; |
---|
| 1143 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1144 | break; |
---|
| 1145 | |
---|
| 1146 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1147 | case RADIO3_RSSIDATA: |
---|
| 1148 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
| 1149 | |
---|
| 1150 | /* |
---|
| 1151 | memcpy |
---|
| 1152 | ( |
---|
| 1153 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1154 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
| 1155 | 1024 |
---|
| 1156 | ); |
---|
| 1157 | */ |
---|
| 1158 | memcpy |
---|
| 1159 | ( |
---|
| 1160 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1161 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO3 + 4*rxArg0),\ |
---|
| 1162 | 1024 |
---|
| 1163 | ); |
---|
| 1164 | |
---|
| 1165 | |
---|
| 1166 | //if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0); |
---|
| 1167 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0)); |
---|
| 1168 | |
---|
| 1169 | sendPtr32[0] = packetNo + 1; |
---|
| 1170 | sendPtr32[1] = ACK; |
---|
| 1171 | sendPtr32[2] = command; |
---|
| 1172 | sendPtr32[3] = rxArg0; |
---|
| 1173 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1174 | break; |
---|
| 1175 | |
---|
| 1176 | case RADIO4_RSSIDATA: |
---|
| 1177 | memcpy |
---|
| 1178 | ( |
---|
| 1179 | (unsigned int *)(sendPtr32 + 4), \ |
---|
| 1180 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO4 + 4*rxArg0),\ |
---|
| 1181 | 1024 |
---|
| 1182 | ); |
---|
| 1183 | sendPtr32[0] = packetNo + 1; |
---|
| 1184 | sendPtr32[1] = ACK; |
---|
| 1185 | sendPtr32[2] = command; |
---|
| 1186 | sendPtr32[3] = rxArg0; |
---|
| 1187 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
| 1188 | break; |
---|
| 1189 | #endif |
---|
| 1190 | |
---|
| 1191 | |
---|
| 1192 | case RADIO1TXBUFF_TXEN: |
---|
| 1193 | warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(1); |
---|
| 1194 | |
---|
| 1195 | sendACK(packetNo, command); |
---|
| 1196 | break; |
---|
| 1197 | |
---|
| 1198 | case RADIO2TXBUFF_TXEN: |
---|
| 1199 | warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(1); |
---|
| 1200 | |
---|
| 1201 | sendACK(packetNo, command); |
---|
| 1202 | break; |
---|
| 1203 | |
---|
| 1204 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1205 | case RADIO3TXBUFF_TXEN: |
---|
| 1206 | warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(1); |
---|
| 1207 | |
---|
| 1208 | sendACK(packetNo, command); |
---|
| 1209 | break; |
---|
| 1210 | |
---|
| 1211 | case RADIO4TXBUFF_TXEN: |
---|
| 1212 | warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(1); |
---|
| 1213 | |
---|
| 1214 | sendACK(packetNo, command); |
---|
| 1215 | break; |
---|
| 1216 | #endif |
---|
| 1217 | |
---|
| 1218 | case RADIO1TXBUFF_TXDIS: |
---|
| 1219 | warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0); |
---|
| 1220 | |
---|
| 1221 | sendACK(packetNo, command); |
---|
| 1222 | break; |
---|
| 1223 | |
---|
| 1224 | case RADIO2TXBUFF_TXDIS: |
---|
| 1225 | warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0); |
---|
| 1226 | |
---|
| 1227 | sendACK(packetNo, command); |
---|
| 1228 | break; |
---|
| 1229 | |
---|
| 1230 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1231 | case RADIO3TXBUFF_TXDIS: |
---|
| 1232 | warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0); |
---|
| 1233 | |
---|
| 1234 | sendACK(packetNo, command); |
---|
| 1235 | break; |
---|
| 1236 | |
---|
| 1237 | case RADIO4TXBUFF_TXDIS: |
---|
| 1238 | warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0); |
---|
| 1239 | |
---|
| 1240 | sendACK(packetNo, command); |
---|
| 1241 | break; |
---|
| 1242 | #endif |
---|
| 1243 | |
---|
| 1244 | case RADIO1RXBUFF_RXEN: |
---|
| 1245 | warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(1); |
---|
| 1246 | |
---|
| 1247 | sendACK(packetNo, command); |
---|
| 1248 | break; |
---|
| 1249 | |
---|
| 1250 | case RADIO2RXBUFF_RXEN: |
---|
| 1251 | warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(1); |
---|
| 1252 | |
---|
| 1253 | sendACK(packetNo, command); |
---|
| 1254 | break; |
---|
| 1255 | |
---|
| 1256 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1257 | case RADIO3RXBUFF_RXEN: |
---|
| 1258 | warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(1); |
---|
| 1259 | |
---|
| 1260 | sendACK(packetNo, command); |
---|
| 1261 | break; |
---|
| 1262 | |
---|
| 1263 | case RADIO4RXBUFF_RXEN: |
---|
| 1264 | warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(1); |
---|
| 1265 | |
---|
| 1266 | sendACK(packetNo, command); |
---|
| 1267 | break; |
---|
| 1268 | #endif |
---|
| 1269 | |
---|
| 1270 | case RADIO1RXBUFF_RXDIS: |
---|
| 1271 | warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0); |
---|
| 1272 | |
---|
| 1273 | sendACK(packetNo, command); |
---|
| 1274 | break; |
---|
| 1275 | |
---|
| 1276 | case RADIO2RXBUFF_RXDIS: |
---|
| 1277 | warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0); |
---|
| 1278 | |
---|
| 1279 | sendACK(packetNo, command); |
---|
| 1280 | break; |
---|
| 1281 | |
---|
| 1282 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1283 | case RADIO3RXBUFF_RXDIS: |
---|
| 1284 | warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0); |
---|
| 1285 | |
---|
| 1286 | sendACK(packetNo, command); |
---|
| 1287 | break; |
---|
| 1288 | |
---|
| 1289 | case RADIO4RXBUFF_RXDIS: |
---|
| 1290 | warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0); |
---|
| 1291 | |
---|
| 1292 | sendACK(packetNo, command); |
---|
| 1293 | break; |
---|
| 1294 | #endif |
---|
| 1295 | |
---|
| 1296 | case RX_DONECHECK: |
---|
| 1297 | |
---|
| 1298 | sendPtr32[0] = packetNo + 1; |
---|
| 1299 | sendPtr32[1] = ACK; |
---|
| 1300 | sendPtr32[2] = command; |
---|
| 1301 | |
---|
| 1302 | if(warplab_mimo_ReadReg_CaptureDone(WARPLAB_BASEADDR) == 0) |
---|
| 1303 | sendPtr32[3] = 0; |
---|
| 1304 | else |
---|
| 1305 | sendPtr32[3] = 1; |
---|
| 1306 | |
---|
| 1307 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1308 | break; |
---|
| 1309 | |
---|
| 1310 | case RX_DONEREADING: |
---|
| 1311 | //warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 1); |
---|
| 1312 | //warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 0); |
---|
| 1313 | |
---|
| 1314 | sendACK(packetNo, command); |
---|
| 1315 | break; |
---|
| 1316 | |
---|
| 1317 | case RX_START: |
---|
| 1318 | //if(DEBUG_LVL > 1) xil_printf("Starting Rx\n"); |
---|
| 1319 | //if(DEBUG_LVL > 1) xil_printf("Starting Rx\n"); |
---|
| 1320 | sendACK(packetNo, command); |
---|
| 1321 | |
---|
| 1322 | if(waitForSync() == 0) |
---|
| 1323 | { |
---|
| 1324 | warplab_buffers_WriteReg_StartCapture(1); |
---|
| 1325 | warplab_AGC_Start(); |
---|
| 1326 | warplab_buffers_WriteReg_StartCapture(0); |
---|
| 1327 | |
---|
| 1328 | //if(DEBUG_LVL > 1) xil_printf("Capture started\n"); |
---|
| 1329 | } |
---|
| 1330 | else |
---|
| 1331 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Rx Capture\n"); |
---|
| 1332 | break; |
---|
| 1333 | |
---|
| 1334 | case TX_START: |
---|
| 1335 | //if(DEBUG_LVL > 1) xil_printf("Starting Tx\n"); |
---|
| 1336 | if(DEBUG_LVL > 1) xil_printf("Starting Tx\n"); |
---|
| 1337 | sendACK(packetNo, command); |
---|
| 1338 | |
---|
| 1339 | if(waitForSync() == 0) |
---|
| 1340 | { |
---|
| 1341 | warplab_buffers_WriteReg_StartTx(1); |
---|
| 1342 | warplab_buffers_WriteReg_StartTx(0); |
---|
| 1343 | //if(DEBUG_LVL > 1) xil_printf("Transmit started\n"); |
---|
| 1344 | } |
---|
| 1345 | else |
---|
| 1346 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Tx\n"); |
---|
| 1347 | break; |
---|
| 1348 | |
---|
| 1349 | case TX_STOP: |
---|
| 1350 | sendACK(packetNo, command); |
---|
| 1351 | |
---|
| 1352 | warplab_buffers_WriteReg_StopTx(1); |
---|
| 1353 | warplab_buffers_WriteReg_StopTx(0); |
---|
| 1354 | |
---|
| 1355 | break; |
---|
| 1356 | |
---|
| 1357 | case TXRX_START: |
---|
| 1358 | if(DEBUG_LVL > 1) xil_printf("Starting TxRX\n"); |
---|
| 1359 | sendACK(packetNo, command); |
---|
| 1360 | |
---|
| 1361 | if(waitForSync() == 0) |
---|
| 1362 | { |
---|
| 1363 | warplab_buffers_WriteReg_StartTxRx(1); |
---|
| 1364 | warplab_buffers_WriteReg_StartTxRx(0); |
---|
| 1365 | } |
---|
| 1366 | else |
---|
| 1367 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling TxRx\n"); |
---|
| 1368 | break; |
---|
| 1369 | |
---|
| 1370 | case READ_AGC_DONE_ADDR: |
---|
| 1371 | sendPtr32[0] = packetNo + 1; |
---|
| 1372 | sendPtr32[1] = ACK; |
---|
| 1373 | sendPtr32[2] = command; |
---|
| 1374 | |
---|
| 1375 | sendPtr32[3] = warplab_mimo_ReadReg_AGCDoneAddr(WARPLAB_BASEADDR); |
---|
| 1376 | |
---|
| 1377 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1378 | break; |
---|
| 1379 | |
---|
| 1380 | case READ_RADIO1AGCDONERSSI: |
---|
| 1381 | sendPtr32[0] = packetNo + 1; |
---|
| 1382 | sendPtr32[1] = ACK; |
---|
| 1383 | sendPtr32[2] = command; |
---|
| 1384 | |
---|
| 1385 | sendPtr32[3] = warplab_mimo_ReadReg_Radio1AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
| 1386 | |
---|
| 1387 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1388 | break; |
---|
| 1389 | |
---|
| 1390 | case READ_RADIO2AGCDONERSSI: |
---|
| 1391 | sendPtr32[0] = packetNo + 1; |
---|
| 1392 | sendPtr32[1] = ACK; |
---|
| 1393 | sendPtr32[2] = command; |
---|
| 1394 | |
---|
| 1395 | sendPtr32[3] = warplab_mimo_ReadReg_Radio2AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
| 1396 | |
---|
| 1397 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1398 | break; |
---|
| 1399 | |
---|
| 1400 | #ifdef WARPLAB_CONFIG_4RF |
---|
| 1401 | case READ_RADIO3AGCDONERSSI: |
---|
| 1402 | sendPtr32[0] = packetNo + 1; |
---|
| 1403 | sendPtr32[1] = ACK; |
---|
| 1404 | sendPtr32[2] = command; |
---|
| 1405 | |
---|
| 1406 | sendPtr32[3] = warplab_mimo_ReadReg_Radio3AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
| 1407 | |
---|
| 1408 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1409 | break; |
---|
| 1410 | |
---|
| 1411 | case READ_RADIO4AGCDONERSSI: |
---|
| 1412 | sendPtr32[0] = packetNo + 1; |
---|
| 1413 | sendPtr32[1] = ACK; |
---|
| 1414 | sendPtr32[2] = command; |
---|
| 1415 | |
---|
| 1416 | sendPtr32[3] = warplab_mimo_ReadReg_Radio4AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
| 1417 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1418 | break; |
---|
| 1419 | #endif |
---|
| 1420 | |
---|
| 1421 | case AGC_RESET: |
---|
| 1422 | warplab_AGC_Reset(); |
---|
| 1423 | sendACK(packetNo, command); |
---|
| 1424 | break; |
---|
| 1425 | |
---|
| 1426 | case READ_AGC_GAINS: |
---|
| 1427 | sendPtr32[0] = packetNo + 1; |
---|
| 1428 | sendPtr32[1] = ACK; |
---|
| 1429 | sendPtr32[2] = command; |
---|
| 1430 | |
---|
| 1431 | sendPtr32[3] = warplab_AGC_GetGains(); |
---|
| 1432 | |
---|
| 1433 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1434 | break; |
---|
| 1435 | |
---|
| 1436 | case SET_AGC_TARGET_dBm: |
---|
| 1437 | agctarget = (int)receivePtr32[2]; |
---|
| 1438 | warplab_AGC_SetTarget(agctarget); |
---|
| 1439 | //xil_printf("agctarget = %d\n",agctarget); |
---|
| 1440 | sendACK(packetNo, command); |
---|
| 1441 | break; |
---|
| 1442 | |
---|
| 1443 | case SET_AGC_DCO_EN_DIS: |
---|
| 1444 | agc_dco_state = (unsigned int)receivePtr32[2]; |
---|
| 1445 | warplab_AGC_SetDCO(agc_dco_state); |
---|
| 1446 | warplab_buffers_WriteReg_DCO_EN_SEL(agc_dco_state); |
---|
| 1447 | //xil_printf("agc_dco_state = %d\n",agc_dco_state); |
---|
| 1448 | sendACK(packetNo, command); |
---|
| 1449 | break; |
---|
| 1450 | |
---|
| 1451 | case SET_AGC_NOISEEST_dBm: |
---|
| 1452 | agcnoiseEst = (int)receivePtr32[2]; |
---|
| 1453 | warplab_AGC_setNoiseEstimate(agcnoiseEst); |
---|
| 1454 | //xil_printf("agctarget = %d\n",agctarget); |
---|
| 1455 | sendACK(packetNo, command); |
---|
| 1456 | break; |
---|
| 1457 | |
---|
| 1458 | case SET_AGC_THRESHOLDS: |
---|
| 1459 | warplab_AGC_WriteReg_Thresholds((unsigned int)receivePtr32[2]); |
---|
| 1460 | sendACK(packetNo, command); |
---|
| 1461 | break; |
---|
| 1462 | |
---|
| 1463 | case SET_AGC_TRIG_DELAY: |
---|
| 1464 | warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)receivePtr32[2]); |
---|
| 1465 | sendACK(packetNo, command); |
---|
| 1466 | break; |
---|
| 1467 | |
---|
| 1468 | case READ_AGC_THRESHOLDS: |
---|
| 1469 | sendPtr32[0] = packetNo + 1; |
---|
| 1470 | sendPtr32[1] = ACK; |
---|
| 1471 | sendPtr32[2] = command; |
---|
| 1472 | |
---|
| 1473 | sendPtr32[3] = warplab_AGC_ReadReg_Thresholds(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1474 | |
---|
| 1475 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
| 1476 | break; |
---|
| 1477 | |
---|
| 1478 | case CLOSE: |
---|
| 1479 | if(DEBUG_LVL > 1) xil_printf("Closing sockets.\n"); |
---|
| 1480 | sendACK(packetNo, command); |
---|
| 1481 | done = 1; |
---|
| 1482 | |
---|
| 1483 | break; |
---|
| 1484 | |
---|
| 1485 | case TX_TEST: |
---|
| 1486 | if(DEBUG_LVL > 1) xil_printf("Starting Tx Test\n"); |
---|
| 1487 | sendACK(packetNo, command); |
---|
| 1488 | |
---|
| 1489 | break; |
---|
| 1490 | |
---|
| 1491 | default: |
---|
| 1492 | if(DEBUG_LVL > 1) xil_printf("Received command (%d) is not recognized. Please retry transmission.\n", command); |
---|
| 1493 | |
---|
| 1494 | sendPtr32[0] = packetNo + 1; |
---|
| 1495 | sendPtr32[1] = NOACK; |
---|
| 1496 | bytesSend = 8; |
---|
| 1497 | xilsock_sendto(sock, sendBuffer, bytesSend, (struct sockaddr *)&addr, alen); |
---|
| 1498 | } |
---|
| 1499 | } |
---|
| 1500 | } |
---|
| 1501 | |
---|
| 1502 | shut_socket(); |
---|
| 1503 | |
---|
| 1504 | return 0; |
---|
| 1505 | } |
---|
| 1506 | |
---|
| 1507 | void sendACK(unsigned int packetNo, unsigned int commandToACK) |
---|
| 1508 | { |
---|
| 1509 | sendPtr32[0] = packetNo + 1; |
---|
| 1510 | sendPtr32[1] = ACK; |
---|
| 1511 | sendPtr32[2] = commandToACK; |
---|
| 1512 | xilsock_sendto(sock, sendBuffer, 12, (struct sockaddr *)&addr, alen); |
---|
| 1513 | return; |
---|
| 1514 | } |
---|
| 1515 | |
---|
| 1516 | unsigned char sevenSegmentMap(unsigned char x) |
---|
| 1517 | { |
---|
| 1518 | switch(x) |
---|
| 1519 | { |
---|
| 1520 | case(0x0) : return 0x007E; |
---|
| 1521 | case(0x1) : return 0x0030; |
---|
| 1522 | case(0x2) : return 0x006D; |
---|
| 1523 | case(0x3) : return 0x0079; |
---|
| 1524 | case(0x4) : return 0x0033; |
---|
| 1525 | case(0x5) : return 0x005B; |
---|
| 1526 | case(0x6) : return 0x005F; |
---|
| 1527 | case(0x7) : return 0x0070; |
---|
| 1528 | case(0x8) : return 0x007F; |
---|
| 1529 | case(0x9) : return 0x007B; |
---|
| 1530 | |
---|
| 1531 | case(0xA) : return 0x0077; |
---|
| 1532 | case(0xB) : return 0x007F; |
---|
| 1533 | case(0xC) : return 0x004E; |
---|
| 1534 | case(0xD) : return 0x007E; |
---|
| 1535 | case(0xE) : return 0x004F; |
---|
| 1536 | case(0xF) : return 0x0047; |
---|
| 1537 | default : return 0x0000; |
---|
| 1538 | } |
---|
| 1539 | } |
---|
| 1540 | |
---|
| 1541 | #define XPAR_EEPROM_CONTROLLER_BASEADDR XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR |
---|
| 1542 | //New TxDCO calibration code |
---|
| 1543 | int warpphy_applyTxDCOCalibration(unsigned int radioSelection) |
---|
| 1544 | { |
---|
| 1545 | #if 0 |
---|
| 1546 | int eepromStatus = 0; |
---|
| 1547 | short calReadback = 0; |
---|
| 1548 | signed short best_I, best_Q; |
---|
| 1549 | unsigned char radioNum; |
---|
| 1550 | Xuint8 memory[8], version, revision, valid, i; |
---|
| 1551 | Xuint16 serial; |
---|
| 1552 | |
---|
| 1553 | //Radio selection will be 0x11111111, 0x22222222, 0x44444444 or 0x88888888 |
---|
| 1554 | // corresponding to radios in slots 1, 2, 3 or 4 |
---|
| 1555 | // We need the slot number to initialize the EEPROM |
---|
| 1556 | radioNum = (radioSelection & 0xF) == 1 ? 1 : ( (radioSelection & 0xF) == 2 ? 2 : ( (radioSelection & 0xF) == 4 ? 3 : 4 ) ); |
---|
| 1557 | if(DEBUG_LVL>2) xil_printf("Applying TxDCO correction for radio %d\n", radioNum); |
---|
| 1558 | |
---|
| 1559 | //Mimic the radio test code, in hopes of a more stable EEPROM read... |
---|
| 1560 | //Choose the EEPROM on the selected radio board; second arg is [0,1,2,3,4] for [FPGA, radio1, radio2, radio3, radio4] |
---|
| 1561 | eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR, 0); |
---|
| 1562 | if(eepromStatus != 0) |
---|
| 1563 | { |
---|
| 1564 | if(DEBUG_LVL>2) xil_printf("EEPROM Select Failed!\n"); |
---|
| 1565 | return -1; |
---|
| 1566 | } |
---|
| 1567 | |
---|
| 1568 | //Initialize the EEPROM controller |
---|
| 1569 | eepromStatus = WarpEEPROM_Initialize((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR); |
---|
| 1570 | if(eepromStatus != 0) |
---|
| 1571 | { |
---|
| 1572 | if(DEBUG_LVL>2) xil_printf("EEPROM Init Returned %x\n", eepromStatus); |
---|
| 1573 | if(DEBUG_LVL>2) xil_printf("EEPROM Init Failed!\n"); |
---|
| 1574 | return -1; |
---|
| 1575 | } |
---|
| 1576 | |
---|
| 1577 | //Select the EEPROM on the current radio board |
---|
| 1578 | eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, radioNum); |
---|
| 1579 | |
---|
| 1580 | if(eepromStatus != 0) |
---|
| 1581 | { |
---|
| 1582 | if(DEBUG_LVL>2) xil_printf("TxDCO: EEPROM error\n"); |
---|
| 1583 | return -1; |
---|
| 1584 | } |
---|
| 1585 | |
---|
| 1586 | //Read the first page from the EERPOM |
---|
| 1587 | WarpEEPROM_ReadMem((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 0, 0, memory); |
---|
| 1588 | version = (memory[0] & 0xE0) >> 5; |
---|
| 1589 | revision = (memory[1] & 0xE0) >> 5; |
---|
| 1590 | valid = memory[1] & 0x1F; |
---|
| 1591 | |
---|
| 1592 | if(DEBUG_LVL>2) xil_printf("\n\nEEPROM Values for Radio Board in Slot %d\n", radioNum); |
---|
| 1593 | |
---|
| 1594 | if(DEBUG_LVL>2) xil_printf(" WARP Radio Board Version %d.%d\n", version, revision); |
---|
| 1595 | |
---|
| 1596 | serial = WarpEEPROM_ReadWARPSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR); |
---|
| 1597 | |
---|
| 1598 | if(DEBUG_LVL>2) xil_printf(" Serial Number (WARP): WR-a-%05d\n", serial); |
---|
| 1599 | |
---|
| 1600 | WarpEEPROM_ReadDSSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, memory); |
---|
| 1601 | if(DEBUG_LVL>2) print(" EEPROM Hard-wired Serial Number: "); |
---|
| 1602 | if(DEBUG_LVL>2){ |
---|
| 1603 | for(i=1;i<7;i++) |
---|
| 1604 | xil_printf(" %x",memory[7-i]); |
---|
| 1605 | xil_printf("\n\n"); |
---|
| 1606 | } |
---|
| 1607 | //Read the Tx DCO values |
---|
| 1608 | calReadback = WarpEEPROM_ReadRadioCal((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 2, 1); |
---|
| 1609 | |
---|
| 1610 | //Scale the stored values |
---|
| 1611 | best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1); |
---|
| 1612 | best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1); |
---|
| 1613 | |
---|
| 1614 | if(DEBUG_LVL>2) xil_printf("TxDCO: Applied values to radio %d - I: %d\tQ: %d\n", radioNum, best_I, best_Q); |
---|
| 1615 | |
---|
| 1616 | //Finally, write the Tx DCO values to the DAC |
---|
| 1617 | WarpRadio_v1_DACOffsetAdj(ICHAN, best_I, radioSelection); |
---|
| 1618 | WarpRadio_v1_DACOffsetAdj(QCHAN, best_Q, radioSelection); |
---|
| 1619 | #endif |
---|
| 1620 | return 0; |
---|
| 1621 | } |
---|
| 1622 | |
---|
| 1623 | |
---|
| 1624 | void warplab_AGC_Reset() |
---|
| 1625 | { |
---|
| 1626 | // Cycle the agc's software reset port |
---|
| 1627 | |
---|
| 1628 | warplab_AGC_WriteReg_SRESET_IN(1); |
---|
| 1629 | usleep(10); |
---|
| 1630 | warplab_AGC_WriteReg_SRESET_IN(0); |
---|
| 1631 | usleep(100); |
---|
| 1632 | |
---|
| 1633 | return; |
---|
| 1634 | } |
---|
| 1635 | |
---|
| 1636 | void warplab_AGC_MasterReset() |
---|
| 1637 | { |
---|
| 1638 | // Cycle the master reset register in the AGC and enable it |
---|
| 1639 | |
---|
| 1640 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
| 1641 | usleep(10); |
---|
| 1642 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
| 1643 | usleep(10); |
---|
| 1644 | warplab_AGC_WriteReg_MRESET_IN(1); |
---|
| 1645 | usleep(10); |
---|
| 1646 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
| 1647 | usleep(10); |
---|
| 1648 | warplab_AGC_WriteReg_AGC_EN(1); |
---|
| 1649 | |
---|
| 1650 | return; |
---|
| 1651 | } |
---|
| 1652 | |
---|
| 1653 | void warplab_AGC_Start() |
---|
| 1654 | { |
---|
| 1655 | // Cycle the agc's packet in port |
---|
| 1656 | warplab_AGC_WriteReg_PACKET_IN(1); |
---|
| 1657 | usleep(10); |
---|
| 1658 | warplab_AGC_WriteReg_PACKET_IN(0); |
---|
| 1659 | usleep(100); |
---|
| 1660 | |
---|
| 1661 | return; |
---|
| 1662 | } |
---|
| 1663 | |
---|
| 1664 | void warplab_AGC_Initialize(int noise_estimate) |
---|
| 1665 | { |
---|
| 1666 | int g_bbset = 0; |
---|
| 1667 | |
---|
| 1668 | // First set all standard parameters |
---|
| 1669 | |
---|
| 1670 | // Turn off both resets and the master enable |
---|
| 1671 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
| 1672 | warplab_AGC_WriteReg_SRESET_IN(0); |
---|
| 1673 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
| 1674 | |
---|
| 1675 | // An adjustment parameter |
---|
| 1676 | warplab_AGC_WriteReg_ADJ(8); |
---|
| 1677 | |
---|
| 1678 | // Timing for the DC-offset correction |
---|
| 1679 | warplab_AGC_WriteReg_DCO_Timing(0x12001000); |
---|
| 1680 | |
---|
| 1681 | // Initial baseband gain setting |
---|
| 1682 | warplab_AGC_WriteReg_GBB_init(52); |
---|
| 1683 | |
---|
| 1684 | // RF gain AGCstate thresholds |
---|
| 1685 | warplab_AGC_WriteReg_Thresholds(0xD5CBA6); |
---|
| 1686 | |
---|
| 1687 | // Overall AGC timing |
---|
| 1688 | warplab_AGC_WriteReg_Timing(0x9A962A28);//0x826E3C0A; |
---|
| 1689 | |
---|
| 1690 | // vIQ and RSSI average lengths |
---|
| 1691 | warplab_AGC_WriteReg_AVG_LEN(0x10F); //103 |
---|
| 1692 | |
---|
| 1693 | // Disable DCO, disable DCO subtraction |
---|
| 1694 | warplab_AGC_WriteReg_Bits(0x0); |
---|
| 1695 | |
---|
| 1696 | // Compute and set the initial g_BB gain value from the noise estimate |
---|
| 1697 | // The initial g_bb sets noise to -19 db, assuming 32 db RF gain |
---|
| 1698 | |
---|
| 1699 | g_bbset = -19 - 32 - noise_estimate; |
---|
| 1700 | warplab_AGC_WriteReg_GBB_init(g_bbset); |
---|
| 1701 | |
---|
| 1702 | // Perform a master reset |
---|
| 1703 | warplab_AGC_MasterReset(); |
---|
| 1704 | |
---|
| 1705 | // Agc is now reset and enabled, ready to go! |
---|
| 1706 | return; |
---|
| 1707 | } |
---|
| 1708 | |
---|
| 1709 | void warplab_AGC_setNoiseEstimate(int noise_estimate) |
---|
| 1710 | { |
---|
| 1711 | int g_bbset; |
---|
| 1712 | |
---|
| 1713 | g_bbset = -19 - 32 - noise_estimate; |
---|
| 1714 | |
---|
| 1715 | warplab_AGC_WriteReg_GBB_init(g_bbset); |
---|
| 1716 | |
---|
| 1717 | return; |
---|
| 1718 | } |
---|
| 1719 | |
---|
| 1720 | unsigned int warplab_AGC_GetGains(void) |
---|
| 1721 | { |
---|
| 1722 | unsigned int gBB_A, gRF_A, gBB_B, gRF_B, gBB_C, gRF_C, gBB_D, gRF_D, gains; |
---|
| 1723 | |
---|
| 1724 | // Get the gains from the registers |
---|
| 1725 | gBB_A = warplab_AGC_ReadReg_GBB_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1726 | gRF_A = warplab_AGC_ReadReg_GRF_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1727 | |
---|
| 1728 | gBB_B = warplab_AGC_ReadReg_GBB_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1729 | gRF_B = warplab_AGC_ReadReg_GRF_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1730 | |
---|
| 1731 | gBB_C = warplab_AGC_ReadReg_GBB_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1732 | gRF_C = warplab_AGC_ReadReg_GRF_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1733 | |
---|
| 1734 | gBB_D = warplab_AGC_ReadReg_GBB_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1735 | gRF_D = warplab_AGC_ReadReg_GRF_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1736 | |
---|
| 1737 | // First concatenate the two radios together, into the gRF register |
---|
| 1738 | // 2 lowest bits are RF, 5 higher bits are BB, last bit is unused |
---|
| 1739 | // Multiply by 2^2, shift gBB right by 2 bits |
---|
| 1740 | |
---|
| 1741 | gRF_A = gRF_A + (gBB_A * 4); |
---|
| 1742 | gRF_B = gRF_B + (gBB_B * 4); |
---|
| 1743 | gRF_C = gRF_C + (gBB_C * 4); |
---|
| 1744 | gRF_D = gRF_D + (gBB_D * 4); |
---|
| 1745 | |
---|
| 1746 | // Multiply by 2^8 shift gRF right by 8 bits |
---|
| 1747 | |
---|
| 1748 | gains = gRF_A + (gRF_B * 256) + (gRF_C * 65536) + (gRF_D * 16777216); |
---|
| 1749 | |
---|
| 1750 | return gains; |
---|
| 1751 | } |
---|
| 1752 | |
---|
| 1753 | void warplab_AGC_SetTarget(unsigned int target) |
---|
| 1754 | { |
---|
| 1755 | warplab_AGC_WriteReg_T_dB(target); |
---|
| 1756 | return; |
---|
| 1757 | } |
---|
| 1758 | |
---|
| 1759 | void warplab_AGC_SetDCO(unsigned int AGCstate) |
---|
| 1760 | { |
---|
| 1761 | // Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active) |
---|
| 1762 | |
---|
| 1763 | unsigned int bits; |
---|
| 1764 | |
---|
| 1765 | bits = warplab_AGC_ReadReg_Bits(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
| 1766 | |
---|
| 1767 | if(AGCstate) |
---|
| 1768 | bits = bits | 0x6; |
---|
| 1769 | else |
---|
| 1770 | bits = bits & 0x1; |
---|
| 1771 | |
---|
| 1772 | warplab_AGC_WriteReg_Bits(bits); |
---|
| 1773 | |
---|
| 1774 | return; |
---|
| 1775 | } |
---|