6 | | The PROM programming file (.mcs file) can be generated via the iMPACT GUI or with the promgen command. |
| 5 | Using the SPI flash for configuration requires 4 steps: |
| 6 | 1. Select the SPI flash for configuration via the config DIP switch |
| 7 | 1. Preparing your .bit file for conversion |
| 8 | 1. Convert your .bit file to a .mcs file |
| 9 | 1. Program the SPI flash with your .mcs file |
| 10 | |
| 11 | These processes are detailed below. |
| 12 | |
| 13 | These instructions have been tested with Xilinx ISE 13.4. |
| 14 | |
| 15 | == Selecting the SPI Flash == |
| 16 | Set the left-most switch in the configuration DIP switch to 1. Refer to the [wiki:HardwareUsersGuides/WARPv3/FPGAConfig WARP v3 User Guide] for details. |
| 17 | |
| 18 | == Preparing the .bit file == |
| 19 | The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process. |
| 20 | |
| 21 | The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the {{{-g ConfigRate}}} bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz. |
| 22 | |
| 23 | To set the CCLK frequency to 33MHz: |
| 24 | * ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33. |
| 25 | * XPS: edit Project -> bitgen.ut, add a line: |
| 26 | {{{ |
| 27 | -g ConfigRate:33 |
| 28 | }}} |
| 29 | |
| 30 | If you're using the SDK, you must update and re-export the bitstream from XPS for the ConfigRate to take effect. |
| 31 | |
| 32 | All the WARP reference and template designs are configured for ConfigRate of 33MHz by default. |
| 33 | |
| 34 | == Creating the .mcs File == |
| 35 | You must convert your .bit file to a .mcs file before it can be written to the SPI flash. There are two methods for this: the iMPACT GUI or on the command line with promgen. |
48 | | === Configuration Clock Frequency === |
49 | | The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process. |
50 | | |
51 | | The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the {{{-g ConfigRate}}} bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz. |
52 | | |
53 | | To set the CCLK frequency to 33MHz: |
54 | | * ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33. |
55 | | * XPS: edit Project -> bitgen.ut, add a line: |
56 | | {{{ |
57 | | -g ConfigRate:33 |
58 | | }}} |
59 | | |
60 | | You will need to re-generate the .mcs file and re-program the SPI flash if you change the CCLK frequency. |