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We are developing a pcore to read RSSI values, with Rice's radio bridge pcore and radio_controller pcore. We only found two gateway ports in Rice's packet detection pcore for each radio card -- 10-bit RSSI data and RSSI_ADC_CLK. From the radio card schematics, we notice there are other control signals, such as RSSI_ADC_HIZ, RSSI_ADC_SLEEP, RSSI_ADC_CLAMP and RSSI_ADC_OTR.
Can we assume these signals are taken care by Rice's radio_bridge pcore, such that we don't need to worry about it?
Second, what are the possible rates for the RSSI ADC? AD9200 is for 2 to 20 MSPS. We notice that, in Rice's model, the RSSI_ADC is fed with 20MHz. We plan to provide USER_RSSI_ADC_CLK with 10 MHz signal, I hope this is fine.
Thanks.
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RSSI_ADC_HIZ, RSSI_ADC_SLEEP and RSSI_ADC_CLAMP are inputs to the AD9200 and are driven by the radio controller core to default values which configure the ADC to its nominal state. RSSI_ADC_OTR is an output from the AD9200 which indicates an out-of-range analog input. This signal is routed from the ADC to the radio bridge, then to the radio controller where its value can be read via a register. Your custom RSSI core can also use this signal; just connect the bridge->controller signal (probably named something like "radio_bridge_slot_1_controller_RSSI_ADC_OTR_radio_controller_0_radio1_RSSI_ADC_OTR") to an input on your custom core.
Our projects clock the RSSI ADC converter at 1/4 the OPB clock, which is 12.5MHz (50MHz/4) in most designs. The RSSI_ADC_CLK signal is produced by using the MSB of a 2-bit counter located in the packet detection core. You can generate your own clock signal if needed. The RSSI_ADC_D signals (the 10-bit data bus) are currently registered in the IOBs using the OPB clock in the radio bridge. This has the potential to cause setup/hold problems, but we haven't actually seen any problems because of this. A future radio_bridge pcore will address this.
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