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Does WARP provide clock control to users, such that a user can change the working frequency of FPGA and DAC, as long as within the range of permission. If so, what are maximums and how to control?
Thanks.
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With the current version of the hardware, the FPGA board has a single 100 MHz oscillator feeding a global clock pin on the FPGA. The FPGA uses a DCM to derive the clock signals used elsewhere in the system. This includes the 50 MHz ADC/DAC clock for the radio board, the 200 MHz PowerPC clock, 100 MHz PLB clock and 50 MHz OPB clock. You can customize the frequencies of all of these clocks by modifying the configuration of the dcm_module in your XPS design.
Future distributions of the FPGA board will include a centralized clock circuit. This circuit will provide five copies of a very clean 40MHz clock. One is driven into a global clock pin on the FPGA. The other four are used to drive the ADC/DACs on radio boards via board-to-board cables (not via traces on the FPGA board). All other clocks in the FPGA can be derived from this 40 MHz input, allowing a PHY (in logic) and the PowerPC processor to operate synchronously with the ADC/DACs. It will still be possible to use the 100 MHz oscillator in other parts of the FPGA.
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Thanks murphpo.
Can I say, the maximum clock rate of FPGA logic is determined by OPB clock? or rather ADC/DAC clock? In sysgen design, we always normalize the minimum sampling period as 1. When we put the design into FPGA, this period of 1 is tied up (looks to me as a slave to) OPB or ADAC?
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It depends on what kind of physical layer architecture you're designing. In the case of our MIMO OFDM PHY, everything is synchronous with the 50 MHz clock that drives both the radio's ADC/DACs and the OPB. This is a property of the architecture we used in the PHY, not a strict requirement of the hardware. It is certainly possible to design a PHY that has two clock domains- one for the bus interface, another for the analog I/O. It would even be possible to decouple the analog I/O clock from the PHY's processing clock with FIFOs or some other clock-domain-crossing buffers.
For your application, I suspect the OFDM PHY will be synchronous with the ADC/DACs, meaning the Sysgen core's system clock will be some multiple (1 or bigger) of the analog I/O clock (50 MHz now, 40 MHz with the real clock circuit later).
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Ok, It is good that we can flexibly control the clock domain.
What we did in Friday was changing the lab 2 a little bit to be a single tone test. The purpose of this is to test the capability of frequency control and power control. Given the DAC is running at 50 MHz, our results are correct. In warp platform, we didn't make any explicit configuration of the DAC/FPGA clock setting during the building process. It happens magically :-).
In another hardware platform (Lyrtech), we have to explicitly programm the clock control to set the FPGA clock before load our design. The clock of ADC/DAC is derived from our design. For example, let the FPGA is working at 50MHz, corresponding to sampling period 1 in sysgen model. If we set the sampling period of the ADC/DAC block as 2, the ADC/DAC will work at 25MHz sampling rate. So, we exactly know where custom design gets the clock source from -- custom design derive its clock from (slave to) the explicit clock control, and ADC/DAC derives its clock from (slave to) custom design.
My understanding now is that, in the current WARP default setup, ADC/DAC and OPB are driven by the same 50MHz clock. The same clock is also the source of any custom pcore we build. Thus, the custom pcore does not derive its clock from either ADAC or OPB. These three parts are equal (no master/slave) in clock control. If we want to have a different clock settings, we have to change the default setting. Right?
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zrcao wrote:
In warp platform, we didn't make any explicit configuration of the DAC/FPGA clock setting during the building process. It happens magically :-). In another hardware platform (Lyrtech), we have to explicitly programm the clock control to set the FPGA clock before load our design.
That's what we like to hear. :-)
If you design a custom pcore using sysgen2opb, there will be a single clock input (opb_clk) that clocks both the OPB interface and the system clock for the sysgen logic. You can connect any clock signal in XPS to this port. We generally use the same signal for the OPB, the ADC/DAC and sysgen2opb cores. In order to customize this, you would need to assign whatever clock signal you want to each peripheral, then customize dcm_modules to produce these clocks as needed.
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LOL.
murphpo wrote:
If you design a custom pcore using sysgen2opb, there will be a single clock input (opb_clk) that clocks both the OPB interface and the system clock for the sysgen logic
Are these two, "clocking the OPB interface (of a custom pcore)" and "clocking the OPB bus", mean the same thing? It seems to me that they are different. Since the bus can only run at one speed given by one source. On the other hand, if I generate two custom pcores separately using sysgen2opb, each of them will have a clock input (opb_clk) to clock its OPB interface. So the OPB bus gets its clock from a source other than pcores, while the opb_clk of each pcore clocks its OPB interface to make sure this pcore can communicate using OPB bus.
Am I right?
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The OPB is a synchronous bus- all peripheral on the bus (masters and slaves) share a single clock signal.
When you use sysgen2opb, the OPB interface is created at the top-level of your sysgen model and is built from sysgen blocks. This means that the core's OPB slave interface and your original sysgen design share a clock (the sysgen master clock), which must be the OPB bus clock.
When you build a project using Base System Builder, this clock signal is named 'sys_clk_s' in XPS. In our OFDM projects, the OPB and PLB run at different speeds, so we usually use the name 'sys_clk_OPB' and 'sys_clk_PLB'. In both cases, all of the clock signals are provided by a dcm_module pcore.
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